Patents by Inventor Masakatsu Maeda

Masakatsu Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10325162
    Abstract: There is provided a detection device that includes: a position estimator that estimates a candidate position of a crosswalk in a movement direction of a vehicle and estimates a length of the crosswalk and an intersecting angle between the crosswalk and a roadway using the candidate position; a corrector that corrects the numbers of periods and widths of two basis functions based on the estimated length of the crosswalk and the estimated intersecting angle, the two basis functions corresponding to intervals of white lines of the crosswalk and are orthogonal to each other; and a crosswalk detector that detects whether or not the crosswalk is present using both image data which include the candidate position and the two corrected basis functions.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: June 18, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masakatsu Maeda, Hirofumi Nishimura, Takahiro Shima, Naoya Yosoku, Yoshito Hirai
  • Publication number: 20170337432
    Abstract: There is provided a detection device that includes: a position estimator that estimates a candidate position of a crosswalk in a movement direction of a vehicle and estimates a length of the crosswalk and an intersecting angle between the crosswalk and a roadway using the candidate position; a corrector that corrects the numbers of periods and widths of two basis functions based on the estimated length of the crosswalk and the estimated intersecting angle, the two basis functions corresponding to intervals of white lines of the crosswalk and are orthogonal to each other; and a crosswalk detector that detects whether or not the crosswalk is present using both image data which include the candidate position and the two corrected basis functions.
    Type: Application
    Filed: May 12, 2017
    Publication date: November 23, 2017
    Inventors: MASAKATSU MAEDA, HIROFUMI NISHIMURA, TAKAHIRO SHIMA, NAOYA YOSOKU, YOSHITO HIRAI
  • Patent number: 9654063
    Abstract: A bias circuit comprises: a first circuit that comprises a first resistor and a decoupling capacitor; a bias voltage generation circuit that comprises a first transistor being connected to the first circuit; one or more switches; a first replica circuit comprising a second circuit and a second transistor, the second circuit comprising a second resistor and a capacitor, the second transistor being connected to the second circuit; a second replica circuit comprising a third transistor; a comparator that makes a comparison between a pseudo-bias voltage and a reference voltage; and a control circuit that controls the one or more switches on the basis of the comparison result to reduce the amount of the current flowing through the first transistor.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: May 16, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yukio Okazaki, Masakatsu Maeda, Shigeki Nakamura, Akinori Daimo
  • Publication number: 20160154099
    Abstract: An object detection apparatus comprises: wireless-signal transmitting-receiving circuitry that transmits a wireless signal to a road mirror among one or more road mirrors provided at predetermined locations and receives a reflected-wave signal reflected by the road mirror, and control circuitry that detects the road mirror among the one or more road mirrors, and detects the presence of a moving object in accordance with (A) the transmitted wireless signal, and (B) the reflected-wave signal, which includes a signal received by the wireless-signal transmitting-receiving circuitry when at least part of the transmitted wireless signal is reflected by the road mirror and then reaches the moving object and is reflected by the moving object and then reaches the road mirror and reflected by the road mirror and then reaches the object detection apparatus.
    Type: Application
    Filed: October 21, 2015
    Publication date: June 2, 2016
    Inventors: YOSHIYUKI SAITO, MASAKATSU MAEDA
  • Publication number: 20160142014
    Abstract: A bias circuit comprises: a first circuit that comprises a first resistor and a decoupling capacitor; a bias voltage generation circuit that comprises a first transistor being connected to the first circuit; one or more switches; a first replica circuit comprising a second circuit and a second transistor, the second circuit comprising a second resistor and a capacitor, the second transistor being connected to the second circuit; a second replica circuit comprising a third transistor; a comparator that makes a comparison between a pseudo-bias voltage and a reference voltage; and a control circuit that controls the one or more switches on the basis of the comparison result to reduce the amount of the current flowing through the first transistor.
    Type: Application
    Filed: October 16, 2015
    Publication date: May 19, 2016
    Inventors: YUKIO OKAZAKI, MASAKATSU MAEDA, SHIGEKI NAKAMURA, AKINORI DAIMO
  • Patent number: 9148089
    Abstract: A transmitting apparatus and transmission method are capable of easily and correctly mixing an in-phase component and a quadrature-phase component in a quadrature modulator. A local signal with a duty ratio of 25% or smaller is generated without using frequency which is a multiple of frequency of the local signal. Without providing switches in series to the outputs of I and Q amplifiers, a duty ratio of 25% or less is obtained. for the local signal, and class-D unit amplifiers are operated such that one of the I amplifier and the Q amplifier is connected to the output side in any state regardless of whether an output power control signal is at an on-level or an off-level. In producing the 25% duty ratio, a local signal with a 50% duty ratio is converted so as to have a duty ratio of 25% by I and Q duty converters.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: September 29, 2015
    Assignee: Panasonic Corporation
    Inventors: Masakatsu Maeda, Masahiro Kumagawa, Hisashi Adachi, Akinori Daimo, Kenichi Mori
  • Patent number: 9130610
    Abstract: A transmission apparatus includes a digital amplifier having a plurality of class-D amplifiers connected in parallel to each other, each of the class-D amplifiers including a logic circuit that processes input signals from two input terminals and outputs the input signals to one of two output terminals, according to a selection signal, and including capacitors connected in series to the two output terminals, respectively, a first selection circuit that outputs either an in-phase component or a quadrature component of a transmission signal to the digital amplifier depending on the selection signal, and a second selection circuit that outputs either an in-phase component carrier signal or a quadrature component carrier signal to the digital amplifier depending on the selection signal.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 8, 2015
    Assignee: Panasonic Corporation
    Inventors: Masakatsu Maeda, Hisashi Adachi, Akinori Daimo, Kenichi Mori
  • Publication number: 20150236727
    Abstract: A transmission apparatus includes a digital amplifier having a plurality of class-D amplifiers connected in parallel to each other, each of the class-D amplifiers including a logic circuit that processes input signals from two input terminals and outputs the input signals to one of two output terminals, according to a selection signal, and including capacitors connected in series to the two output terminals, respectively, a first selection circuit that outputs either an in-phase component or a quadrature component of a transmission signal to the digital amplifier depending on the selection signal, and a second selection circuit that outputs either an in-phase component carrier signal or a quadrature component carrier signal to the digital amplifier depending on the selection signal.
    Type: Application
    Filed: January 28, 2015
    Publication date: August 20, 2015
    Inventors: MASAKATSU MAEDA, HISASHI ADACHI, AKINORI DAIMO, KENICHI MORI
  • Publication number: 20150180418
    Abstract: A transmitting apparatus and transmission method are capable of easily and correctly mixing an in-phase component and a quadrature-phase component in a quadrature modulator. A local signal with a duty ratio of 25% or smaller is generated without using frequency which is a multiple of frequency of the local signal. Without providing switches in series to the outputs of I and Q amplifiers, a duty ratio of 25% or less is obtained. for the local signal, and class-D unit amplifiers are operated such that one of the I amplifier and the Q amplifier is connected to the output side in any state regardless of whether an output power control signal is at an on-level or an off-level. In producing the 25% duty ratio, a local signal with a 50% duty ratio is converted so as to have a duty ratio of 25% by I and Q duty converters.
    Type: Application
    Filed: November 17, 2014
    Publication date: June 25, 2015
    Inventors: MASAKATSU MAEDA, MASAHIRO KUMAGAWA, HISASHI ADACHI, AKINORI DAIMO, KENICHI MORI
  • Patent number: 8921461
    Abstract: An epoxy resin composition for encapsulating a semiconductor chip according to this invention comprises (A) a crystalline epoxy resin, (B) a phenol resin represented by general formula (1): wherein R1 and R2 are independently hydrogen or alkyl having 1 to 4 carbon atoms and two or more R1s or two or more R2s are the same or different; a is integer of 0 to 4; b is integer of 0 to 4; c is integer of 0 to 3; and n is average and is number of 0 to 10, (C) a (co)polymer containing butadiene-derived structural unit or its derivative, and (D) an inorganic filler in the amount of 80 wt % to 95 wt % both inclusive in the total epoxy resin composition.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: December 30, 2014
    Assignee: Sumitomo Bakelite Co., Ltd
    Inventors: Takahiro Kotani, Hidetoshi Seki, Masakatsu Maeda, Kazuya Shigeno, Yoshinori Nishitani
  • Patent number: 8716121
    Abstract: An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti(1-x-y)Si(x)C(y) ternary film of which a composition ratio is within a composition range that is surrounded by two lines and two curves expressed by an expression x=0 (0.35?y?0.5), an expression y=?1.120x+0.5200 (0.1667?x?0.375), an expression y=1.778(x?0.375)2+0.1 (0?x?0.375) and an expression y=?2.504x2?0.5828x+0.5 (0?x?0.1667) and that excludes the line expressed by the expression x=0. The ohmic layer is directly laminated on a surface of a p-type SiC semiconductor.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: May 6, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akinori Seki, Masahiro Sugimoto, Akira Kawahashi, Yasuo Takahashi, Masakatsu Maeda
  • Patent number: 8697803
    Abstract: An epoxy resin composition for encapsulating a semiconductor chip according to this invention comprises (A) a crystalline epoxy resin, (B) a phenol resin represented by general formula (1): wherein R1 and R2 are independently hydrogen or alkyl having 1 to 4 carbon atoms and two or more R1s or two or more R2s are the same or different; a is integer of 0 to 4; b is integer of 0 to 4; c is integer of 0 to 3; and n is average and is number of 0 to 10, (C) a (co)polymer containing butadiene-derived structural unit or its derivative, and (D) an inorganic filler in the amount of 80 wt % to 95 wt % both inclusive in the total epoxy resin composition.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: April 15, 2014
    Assignee: Sumitomo Bakelite Company, Ltd.
    Inventors: Takahiro Kotani, Hidetoshi Seki, Masakatsu Maeda, Kazuya Shigeno, Yoshinori Nishitani
  • Patent number: 8633101
    Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: January 21, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masahiro Sugimoto, Akinori Seki, Akira Kawahashi, Yasuo Takahashi, Masakatsu Maeda
  • Publication number: 20130337608
    Abstract: According to the present invention, a structure of a semiconductor device in which adhesive deposits are reduced and yield is excellent; and a process for manufacturing the same can be provided. A process for manufacturing a semiconductor device according to the present invention includes: a step of arranging plural semiconductor elements (106) on a main surface of a thermal release adhesive layer (mount film); a step of forming an encapsulant layer (108), which encapsulates the plural semiconductor elements (106) on the main surface of the mount film, using a semiconductor-encapsulating resin composition; and a step of peeling off the mount film to expose a lower surface (30) of the encapsulant layer (108) and lower surfaces (20) of the semiconductor elements (106). A contact angle of the lower surface (30) of the encapsulant layer (108) is less than or equal to 70° when measured using formamide after the step of peeling off the mount film.
    Type: Application
    Filed: March 9, 2012
    Publication date: December 19, 2013
    Applicant: SUMITOMO BAKELITE CO., LTD.
    Inventors: Takahiro Kotani, Masakatsu Maeda
  • Patent number: 8531213
    Abstract: The present invention provides a CMOS-inverter-type frequency divider circuit that can further reduce power consumption. The CMOS-inverter-type frequency divider circuit includes: a plurality of CMOS inverters that contribute to realizing a frequency division function; a frequency division control section for performing control such that some or all of the plurality of CMOS inverters are intermittently driven at the respective different timings in accordance with an input signal; and a drive power supplying section for supplying powers for driving the plurality of CMOS inverters, and for, based on state information indicating whether VCO sub band selection or normal transmission is performed, switching some or all of the powers for the plurality of CMOS inverters between the VCO sub band selection and the normal transmission.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: September 10, 2013
    Assignee: Panasonic Corporation
    Inventors: Masakatsu Maeda, Mikihiro Shimada
  • Patent number: 8519067
    Abstract: An epoxy resin composition for encapsulating a semiconductor chip according to this invention comprises (A) a crystalline epoxy resin, (B) a phenol resin represented by general formula (1): wherein R1 and R2 are independently hydrogen or alkyl having 1 to 4 carbon atoms and two or more R1s or two or more R2s are the same or different; a is integer of 0 to 4; b is integer of 0 to 4; c is integer of 0 to 3; and n is average and is number of 0 to 10, (C) a (co)polymer containing butadiene-derived structural unit or its derivative, and (D) an inorganic filler in the amount of 80 wt % to 95 wt % both inclusive in the total epoxy resin composition.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: August 27, 2013
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventors: Takahiro Kotani, Hidetoshi Seki, Masakatsu Maeda, Kazuya Shigeno, Yosinori Nishitani
  • Patent number: 8508303
    Abstract: A digital FLL/PLL is provided which is capable of converging an oscillation frequency from a VCO to a desired frequency at a high speed even without setting a damping factor corresponding to each VCO gain. A digital FLL/PLL of the present invention includes: a comparator for comparing a channel signal to a loopback signal having an oscillation frequency to generate a signal error; a digital loop filter for generating a control voltage that determines the oscillation frequency, on the basis of the signal error; a VCO for controlling an oscillation frequency on the basis of the control voltage; a loopback path through which the oscillation frequency generated by the VCO is outputted as the loopback signal to the comparator; and a control section for monitoring the signal error, and controlling the digital loop filter such that the oscillation frequency of the VCO becomes a stationary state, when detecting that the signal error meets a predetermined condition after the channel signal is switched.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: August 13, 2013
    Assignee: Panasonic Corporation
    Inventor: Masakatsu Maeda
  • Patent number: 8477870
    Abstract: Provided is a transmitter including a polar modulation circuit which adjusts a timing lag between an amplitude component and a phase component more accurately than a conventional art. The polar modulation circuit includes: a first calculator for performing an exclusive OR logical operation between the amplitude component before and after being inputted to the first processing section; a second calculator for performing an exclusive OR logical operation between the phase component before and after being inputted to the second processing section; and a delay fluctuation detection/compensation section for obtaining a delay time of the amplitude component based on an amount of output accumulation of the first calculator; obtaining a delay time of the phase component based on an amount of output accumulation of the second calculator; detecting an amount of delay fluctuation by using the delay times; and adjusting timings of the amplitude component and the phase component.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: July 2, 2013
    Assignee: Panasonic Corporation
    Inventor: Masakatsu Maeda
  • Patent number: 8433267
    Abstract: An amplitude modulator comprises: a signal processing section for receiving a source signal for wide bandwidth use, splitting the source signal into two source signals for lower frequency use and for higher frequency use, respectively, signal processing the two source signals individually, and outputting a lower-frequency-use source signal and a higher-frequency-use source signal; a first modulation section for modulating the lower-frequency-use source signal and outputting a lower-frequency-use modulation signal; a second modulation section for modulating the higher-frequency-use source signal and outputting a higher-frequency-use modulation signal; a synthesis output section for inputting the lower-frequency-use modulation signal to a first input terminal, the input thereof causing extraction of only a lower-frequency component, for inputting the higher-frequency-use modulation signal to a second input terminal, the input thereof causing extraction of only a higher-frequency component, for synthesizing the
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: April 30, 2013
    Assignee: Panasonic Corporation
    Inventors: Masakatsu Maeda, Taichi Ikedo
  • Patent number: 8324326
    Abstract: An epoxy resin composition for encapsulating a semiconductor chip according to this invention comprises (A) a crystalline epoxy resin, (B) a phenol resin represented by general formula (1): wherein R1 and R2 are independently hydrogen or alkyl having 1 to 4 carbon atoms and two or more R1s or two or more R2s are the same or different; a is integer of 0 to 4; b is integer of 0 to 4; c is integer of 0 to 3; and n is average and is number of 0 to 10, (C) a (co)polymer containing butadiene-derived structural unit or its derivative, and (D) an inorganic filler in the amount of 80 wt % to 95 wt % both inclusive in the total epoxy resin composition.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: December 4, 2012
    Assignee: Sumitomo Bakelite Company, Ltd.
    Inventors: Takahiro Kotani, Hidetoshi Seki, Masakatsu Maeda, Kazuya Shigeno, Yoshinori Nishitani