Patents by Inventor Masakatsu Maeda

Masakatsu Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7839230
    Abstract: Provided is a PLL oscillation circuit that can reduce the variability of modulation sensitivity of a VCO 101 and obtain a desired output amplitude quickly with high precision. An amplitude detector 103 detects an output amplitude of the VCO 101. An amplitude controller 105 controls a current value of a variable current source 109 so as to have an output amplitude of the VCO 101 detected by the amplitude detector 103 to be a desired amplitude. A LPF 108 is connected between the amplitude controller 105 and the variable current source 109. A switch 107 connects or disconnects the LPF 108 between the amplitude controller 105 and the variable current source 109. The amplitude controller 105 is connected to the variable current source 109 through either the LPF 108 or the switching switch 107.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: November 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Masakatsu Maeda, Takayuki Tsukizawa, Hiroyuki Yoshikawa, Shunsuke Hirano
  • Patent number: 7825422
    Abstract: A ceramic substrate for mounting a light emitting element. The ceramic substrate has a placement surface for placing a light emitting element having an electrode; and an electrode electrically-connected with the electrode of the light emitting element, wherein the ceramic substrate comprises a substrate body consisting of a nitride ceramics; and a coat layer coating at least a part of a surface of the substrate body and consisting of a ceramics different from the nitride ceramics forming the substrate body; and the coat layer has an optical reflectance of 50% or more for any light having a wavelength of from 300 to 800 nm, which can increase a luminance of the light emitting element by reflecting the light emitted from the element efficiently with certainty, and which has a high heat radiation property; and a manufacturing method therefor.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: November 2, 2010
    Assignee: Tokuyama Corporation
    Inventors: Masakatsu Maeda, Yasuyuki Yamamoto
  • Publication number: 20100259160
    Abstract: An insulating material high both in thermal conductivity and light reflectance, and a submount high in heat radiatability for mounting an LED element thereon, capable of raising a light utilization factor and quickly radiating heat generated from the element. For example, used as a substrate material of a submount is a nitride sintered body having a reflectance of light in the wavelength region of from 350 nm to 800 nm of 50% or more and a reflectance of light with a wavelength of 700 nm of 60% or more, obtained by sintering a preform consisting of a composition containing 100 parts by mass of aluminum nitride powder and 0.5 to 10 parts by mass of a compound containing an alkaline earth metal such as 3CaO×Al2O3 in an inert atmosphere containing a specific quantity of carbon vapor, or by burning a coat of a nitride paste applied on a base substrate having a heat resistance at a predetermined temperature.
    Type: Application
    Filed: April 26, 2010
    Publication date: October 14, 2010
    Applicant: Tokuyama Corporation
    Inventors: Yasuyuki YAMAMOTO, Yukihiro KANECHIKA, Masakatsu MAEDA
  • Publication number: 20100183898
    Abstract: A metallized substrate having, disposed in the order mentioned: a ceramics substrate; a high-melting point metal layer; a base nickel plating layer; a layered nickel-phosphorous plating layer; a diffusion-inhibiting plating layer; and a gold plating layer. The base nickel plating layer being any one of a nickel plating layer, a nickel-boron plating layer, or a nickel-cobalt plating layer. The diffusion-inhibiting plating layer being any one of a columnar nickel-phosphorous plating layer, a palladium-phosphorous plating layer, or a palladium plating layer. According to the above composition, even after heating the semiconductor chips in a mounted state, the metallized substrate can make the connection strength of wire bonding favorable.
    Type: Application
    Filed: June 10, 2008
    Publication date: July 22, 2010
    Applicant: TOKUYAMA CORPORATION
    Inventors: Tetsuo Imai, Osamu Yatabe, Masakatsu Maeda
  • Publication number: 20100178461
    Abstract: A fabrication method for metallized a ceramics substrate including the steps of: forming a first conductive paste layer containing metallic powder on a sintered ceramics substrate; forming a second conductive paste layer containing metallic powder of which average particle diameter is different from that of metallic powder constituting the first conductive paste layer; and forming a first conductive layer and a second conductive paste layer. The surface roughness of the first conductive layer and the second conductive layer is different. By this method, it is possible to secure airtightness of the metallized ceramics substrate even if it is a multilayered substrate having a plurality of metallized layers.
    Type: Application
    Filed: January 23, 2007
    Publication date: July 15, 2010
    Inventors: Yasuyuki Yamamoto, Osamu Yatabe, Masakatsu Maeda
  • Patent number: 7742543
    Abstract: A transmission circuit alleviates the frequency characteristics of a group delay and an attenuation amount in a transmission signal band and expands a dynamic range to a high frequency band. A ladder-type resistance-type attenuator includes switching elements, 2R resistor elements and R resistor elements. The 2R and R resistor elements are respectively connected to variable capacitor elements in parallel. The variable attenuator having such a connection structure is connected to an amplitude modulation loop of the transmission circuit. By controlling the capacitance value of the variable capacitor elements using the capacitance value control section when the switching elements are ON/OFF switched based on the transmission power control signal, the influence of parasitic capacitances of the variable capacitor elements is suppressed and the group delay between the amplitude modulation and the phase modulation is reduced.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: June 22, 2010
    Assignee: Panasonic Corporation
    Inventor: Masakatsu Maeda
  • Patent number: 7737461
    Abstract: A light-emitting element storing package which ensures the efficient reflection of light emitted by a light-emitting element by a reflector frame and thereby improves the brightness of the emitted light, and a method of manufacturing the same are provided. In a light-emitting element storing package includes: an insulating substrate consisting of a ceramic board, a reflector frame composed of a ceramic material, joined to the upper surface of the substrate along its outer edge and having an inner wall surface defining a light-reflecting surface, and a wiring pattern layer formed on the upper surface of the substrate for connection with a light-emitting element, a light-emitting element storing concave portion, which is defined by the substrate and the reflector frame, and in which the light-emitting element is mounted on the wiring pattern layer, the reflector frame is mainly composed of nitride ceramics and its light-reflecting surface is composed of white ceramics.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: June 15, 2010
    Assignee: Tokuyama Corporation
    Inventors: Masakatsu Maeda, Yasuyuki Yamamoto, Yukihiro Kanechika
  • Patent number: 7734263
    Abstract: A transmission circuit operates with high efficiency and low distortion. An amplitude and phase extraction section extracts amplitude data and phase data from input data. A phase modulation section phase-modulates the phase data to output a resultant signal as a phase-modulated signal. An amplifier section amplifies the phase-modulated signal to output a resultant signal as a transmission signal. An amplitude control section supplies, to the amplifier section, a voltage controlled in accordance with an AC component represented by a fluctuation component of the amplitude data and a DC component represented by an average value level of the fluctuation component of the amplitude data.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: June 8, 2010
    Assignee: Panasonic Corporation
    Inventors: Masakatsu Maeda, Taichi Ikedo
  • Patent number: 7718456
    Abstract: A package for housing a light-emitting element wherein a via hole for wiring provided so as to pass through an insulating substrate is arranged in such a manner that it is positioned under a reflector frame; a method for manufacturing the above package for housing a light-emitting element which comprises the steps of separately providing a green sheet for the substrate and a green sheet for the frame, causing a paste containing a ceramic powder to be present between the two green sheets to bind them, and subjecting them to degreasing and sintering, to thereby integrate them.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: May 18, 2010
    Assignee: Tokuyama Corporation
    Inventors: Masakatsu Maeda, Yasuyuki Yamamoto
  • Publication number: 20100102332
    Abstract: A method of forming an Ohmic contact on a P-type 4H—SiC and an Ohmic contact formed by the same are provided. A method of forming an Ohmic contact on a P-type 4H—SiC substrate including a deposition step of successively depositing a 1 to 60 nm thick first Al layer, Ti layer, and second Al layer on a P-type 4H—SiC substrate and an alloying step of forming an alloy layer between the SiC substrate and the Ti layer through the first Al layer by heat treatment in a nonoxidizing atmosphere. An Ohmic contact on a P-type 4H—SiC substrate formed by this method is also provided.
    Type: Application
    Filed: March 13, 2008
    Publication date: April 29, 2010
    Applicants: OSAKA UNIVERSITY, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yasuo Takahashi, Masakatsu Maeda, Akinori Seki, Akira Kawahashi, Masahiro Sugimoto
  • Publication number: 20100065310
    Abstract: A method for manufacturing a substrate chip including the steps of: setting the thickness of at least a part of a metal wiring pattern unit provided on the raw substrate to be 0.1 ?m to 5 ?m; forming a groove for creating at least a crack in the surface of the ceramic substrate along a planned cutting line which passes through the part of the metal wiring pattern unit by using a cutting wheel having a cutter blade being formed into substantially V shape in cross section along the circumferential portion of the disk rotating wheel; and cutting the raw substrate by giving load from just behind of the groove. When manufacturing metallized ceramic substrate chips by cutting (dividing) the ceramic substrate on the surface of which wiring patterns made of a metal film is formed, the method is capable of effectively using the base material, inhibiting defects in the metallized portion, and efficiently manufacturing the substrate chips in high yield.
    Type: Application
    Filed: November 29, 2007
    Publication date: March 18, 2010
    Inventors: Yasuyuki Yamamoto, Kouichi Yamamoto, Masakatsu Maeda
  • Publication number: 20100015468
    Abstract: A method for manufacturing metallized aluminum nitride substrate. The method includes: Step A for forming a high-melting point metal layer over a sintered aluminum nitride substrate; Step B for forming over the high-melting point metal layer an intermediate metal layer of at least one selected from the group of: nickel, copper, copper-silver, copper-tin, and gold by plate processing; and Step C for forming a surface metal layer containing silver as a main component over the intermediate metal layer by coating a silver paste whose glass component content is 1 mass % or less and firing under nonoxidizing atmosphere. By this method, it is capable of forming a glass component-free silver layer which is adhered at a high degree of adhesion strength onto the high-melting point metal layer formed over the aluminum nitride substrate as a top face by thick-film method using a silver paste which makes thick-membrane forming easier.
    Type: Application
    Filed: December 21, 2007
    Publication date: January 21, 2010
    Inventors: Yasuyuki Yamamoto, Masakatsu Maeda, Osamu Yatabe
  • Publication number: 20100012368
    Abstract: A method for manufacturing a ceramic substrate having a via hole(s) and a surface wiring pattern electrically connected to the via hole(s). The method includes: preparing a sintered ceramic substrate having a via hole(s); forming over the sintered ceramic substrate a sintered ceramic layer having a hole(s) or opening(s) whose bottom is configured to be at least a part of an exposed end surface of the via hole(s) by post-firing method; forming inside the hole(s) or opening(s) a conductive portion which electrically connects the surface of the sintered ceramic layer and the via hole(s); and forming over the surface of the sintered ceramic layer a surface wiring pattern electrically connected to the conductive portion.
    Type: Application
    Filed: September 5, 2007
    Publication date: January 21, 2010
    Inventors: Yasuyuki Yamamoto, Ken Sugawara, Masakatsu Maeda
  • Publication number: 20100000768
    Abstract: A metallized ceramics substrate including: a ceramics body; a wiring pattern formed on one surface of the ceramics body; and a lead electrically-connected to the wiring pattern. The ceramics body has a through-hole, the lead penetrates the through-hole and sticks out from another surface of the ceramics body, and the lead is fixed by filling an electroconductive filler between the lead and the through-hole for keeping airtightness. The metallized ceramics substrate does not cause a problem of interlayer peeling and is excellent in airtightness and electric conductivity.
    Type: Application
    Filed: February 7, 2007
    Publication date: January 7, 2010
    Inventors: Masakatsu Maeda, Yasuyuki Yamamoto
  • Publication number: 20090289723
    Abstract: Provided is a PLL oscillation circuit that can reduce the variability of modulation sensitivity of a VCO 101 and obtain a desired output amplitude quickly with high precision. An amplitude detector 103 detects an output amplitude of the VCO 101. An amplitude controller 105 controls a current value of a variable current source 109 so as to have an output amplitude of the VCO 101 detected by the amplitude detector 103 to be a desired amplitude. A LPF 108 is connected between the amplitude controller 105 and the variable current source 109. A switch 107 connects or disconnects the LPF 108 between the amplitude controller 105 and the variable current source 109. The amplitude controller 105 is connected to the variable current source 109 through either the LPF 108 or the switching switch 107.
    Type: Application
    Filed: May 20, 2009
    Publication date: November 26, 2009
    Inventors: Masakatsu MAEDA, Takayuki TSUKIZAWA, Hiroyuki YOSHIKAWA, Shunsuke HIRANO
  • Patent number: 7609123
    Abstract: Transistors M11 and M12 are cross-coupled to each other so as to form a negative resistance circuit. First and second variable capacitor sections 10 and 20 are connected in parallel with an inductor circuit so as to form a parallel resonant circuit. A first reference voltage Vref1 and a control voltage VT1 corresponding to a carrier wave component are fed to both terminals, respectively, of each of variable capacitors VC11 and VC12 included in the first variable capacitor section 10. A second reference voltage Vref2 and a control voltage VT2 corresponding to a modulated wave component are fed to both terminals, respectively, of each of variable capacitors VC21 and VC22 included in the second variable capacitor section 20.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: October 27, 2009
    Assignee: Panasonic Corporation
    Inventor: Masakatsu Maeda
  • Patent number: 7595702
    Abstract: A modulation apparatus 24 comprises a monitoring section 207 operable to monitor information about a control voltage applied to a VCO 201 as control voltage information, during any period, when a low-frequency signal having a frequency within a loop band of a PLL circuit is input at least before an LPF 209, a correction table storing section 206 operable to associate the control voltage information monitored by the monitoring section 207 as information about a control voltage after correction with information about a control voltage before correction, and store the associated information as a correction table, and a correction section 204 operable to correct a control voltage applied to the VCO 201 based on the correction table stored in the correction table storing section.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: September 29, 2009
    Assignee: Panasonic Corporation
    Inventor: Masakatsu Maeda
  • Publication number: 20090233435
    Abstract: A method is set forth of forming an ohmic electrode having good characteristics on a SiC semiconductor layer. In the method, a Ti-layer and an Al-layer are formed on a surface of the SiC substrate. The SiC substrate having the Ti-layer and the Al-layer is maintained at a temperature that is higher than or equal to a first temperature and lower than a second temperature until all Ti in the Ti-layer has reacted with Al. The first temperature is the minimum temperature of a temperature zone at which the Ti reacts with the Al to form Al3Ti, and the second temperature is the minimum temperature of a temperature zone at which the Al3Ti reacts with SiC to form Ti3SiC2. As a result of this maintaining of temperature step, an Al3Ti-layer is formed on the surface of the SiC substrate. The method also comprises further heating the SiC substrate having the Al3Ti-layer to a temperature that is higher than the second temperature.
    Type: Application
    Filed: September 21, 2007
    Publication date: September 17, 2009
    Inventors: Akira Kawahashi, Masahiro Sugimoto, Akinori Seki, Masakatsu Maeda, Yasuo Takahashi
  • Patent number: 7587180
    Abstract: An FM modulator measuring an f-V characteristic of a voltage controlled oscillator in a reduced time period. In the FM modular a characteristic measurement time control section 110 notifies a correction section 108 of a time at which a measurement of the f-V characteristic of a voltage controlled oscillator 103 is to start and a time at which the measurement of the f-V characteristic of the voltage controlled oscillator 103 is to and while a carrier wave frequency is being changed to a predetermined frequency. Thus, the correction section 108 measures the f-V characteristic of the voltage controlled oscillator 103 in a reduced time period.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: September 8, 2009
    Assignee: Panasonic Corporation
    Inventors: Masakatsu Maeda, Kaoru Ishida
  • Publication number: 20090115466
    Abstract: A semiconductor apparatus includes a signal source 7 that outputs a signal of predetermined frequency, a frequency divider 15 that receives the output signal of the signal source and is capable of switching the output signal to two or more frequency division ratios, a delta-sigma modulator 16 that controls the frequency division ratio of the frequency divider, and a bandpass filter 17 that receives an output of the frequency divider. The frequency of the input signal of the frequency divider is divided by the frequency division ratio controlled by the delta-sigma modulator, and quantization noise appearing in the output of the frequency divider generated by the delta-sigma modulator is attenuated with the bandpass filter. The semiconductor apparatus easily can convert a signal output by a single signal source to a signal of predetermined frequency and supply a plurality of signals of predetermined frequency using a simple configuration with reduced chip size.
    Type: Application
    Filed: June 27, 2006
    Publication date: May 7, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Masakatsu Maeda