Patents by Inventor Masakatsu Maeda

Masakatsu Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060022726
    Abstract: A loop filter which is a component of a PLL circuit includes a switching element for switching a capacitance value which connects and disconnects a second capacitive element to a first capacitive element according to a natural angular frequency switching signal, and a switching element for switching a resistance value which short-circuits and opens between both ends of a resistance element according to a natural angular frequency switching signal in order to keep a damping factor at a constant value. It further includes an operational amplifier for charging the second capacitive element at the same potential as the first capacitive element when the second capacitive element is isolated from the first capacitive element.
    Type: Application
    Filed: July 26, 2005
    Publication date: February 2, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Masakatsu Maeda
  • Publication number: 20050231295
    Abstract: A voltage controlled oscillator apparatus includes at least two voltage controlled oscillators, each of the voltage controlled oscillators being formed on a semiconductor substrate and having an LC-resonant circuit including a three-terminal inductor or a two-terminal inductor, and a continuously variable capacitor, and an amplifier including n-channel transistors or n-channel transistors and p-channel transistors. Two of the three-terminal or two-terminal inductors constructing the first and second voltage controlled oscillators have a coil shape formed with a wiring layer of an integrated circuit formed on the semiconductor substrate, and one of the three-terminal or two-terminal inductors has such a shape that its inductance value differs from that of the other of the three-terminal or two-terminal inductors, and is disposed in a region inside of the other of the three-terminal or two-terminal inductors with respect to its planar shape.
    Type: Application
    Filed: April 1, 2005
    Publication date: October 20, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masakatsu Maeda
  • Publication number: 20050156277
    Abstract: There is provided a semiconductor device, wherein a digital circuit region and an analog circuit region are located independently. A power supply wiring and a ground wiring are placed on the periphery of each circuit region and are connected to elements in each circuit region. A MOS capacitor is formed under the power supply wiring and the ground wiring. The terminals of the MOS capacity are connected to the power supply wiring and the ground wiring. Pads are placed in each circuit region surrounded by the power supply wiring, the ground wiring, and the MOS capacitor and are connected to the elements of each circuit region.
    Type: Application
    Filed: December 15, 2004
    Publication date: July 21, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hideo Nakano, Shoji Yoshida, Masakatsu Maeda
  • Publication number: 20040265596
    Abstract: Outstanding YAG laser marking characteristics can be obtained without electric defects such as a short circuit and leak current and without deforming gold wires by using an epoxy resin composition for semiconductor sealing comprising an epoxy resin, a phenol resin, an inorganic filler, a curing accelerator, and a carbon precursor having a specific electric resistivity in a semiconductor region of 1×102·cm or more but less than 1×107·cm as essential components, wherein the amounts of the inorganic filler and the carbon precursor in the epoxy resin composition are respectively 65-92 wt % and 0.1-5.0 wt %.
    Type: Application
    Filed: April 12, 2004
    Publication date: December 30, 2004
    Applicant: SUMITOMO BAKELITE CO., LTD.
    Inventor: Masakatsu Maeda
  • Publication number: 20040081266
    Abstract: A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
    Type: Application
    Filed: December 8, 2003
    Publication date: April 29, 2004
    Inventors: Hisashi Adachi, Toshifumi Nakatani, Hiroaki Kosugi, Shunsuke Hirano, Masakatsu Maeda
  • Patent number: 6717998
    Abstract: A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: April 6, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisashi Adachi, Toshifumi Nakatani, Hiroaki Kosugi, Masakatsu Maeda, Shunsuke Hirano
  • Publication number: 20020061086
    Abstract: A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to output data from a multiplier, and outputs resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step, and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step, and outputs resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to average data of the period.
    Type: Application
    Filed: December 12, 2000
    Publication date: May 23, 2002
    Inventors: Hisashi Adachi, Toshifumi Nakatani, Hiroaki Kosugi, Masakatsu Maeda, Shunsuke Hirano
  • Patent number: 5665473
    Abstract: A package for mounting a semiconductor device comprises a base plate and a conductive layer laminated onto the base plate via an adhesive layer. The modulus of elasticity at 25.degree. C. of the adhesive layer is 10 kg/mm.sup.2 or less.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: September 9, 1997
    Assignee: Tokuyama Corporation
    Inventors: Tokio Okoshi, Yuka Kato, Hideki Okoshi, Kenichiro Miyahara, Masakatsu Maeda
  • Patent number: D341515
    Type: Grant
    Filed: March 13, 1992
    Date of Patent: November 23, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Hamada, Masakatsu Maeda, Kumiko Ito, Takako Tsubaki
  • Patent number: D341516
    Type: Grant
    Filed: March 13, 1992
    Date of Patent: November 23, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Hamada, Masakatsu Maeda, Kumiko Ito
  • Patent number: D357384
    Type: Grant
    Filed: August 25, 1993
    Date of Patent: April 18, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masakatsu Maeda, Norihisa Yoshida
  • Patent number: D360509
    Type: Grant
    Filed: May 5, 1994
    Date of Patent: July 18, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masakatsu Maeda, Rika Tezuchi
  • Patent number: D374322
    Type: Grant
    Filed: July 31, 1995
    Date of Patent: October 1, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masakatsu Maeda, Fumioki Ichihara
  • Patent number: D391721
    Type: Grant
    Filed: January 30, 1997
    Date of Patent: March 3, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Osamu Kondo, Toru Abe, Masakatsu Maeda