Abstract: A catalyst ceramic body employing a directly supporting carrier, wherein particle growth due to aggregation of the catalyst particles during loading of the catalyst is suppressed to yield fine particles, thereby improving the purification performance. According to the invention, the base material is cordierite with a portion of its constituent elements substituted, and when a catalyst component such as Pt is to be supported on a ceramic carrier capable of directly supporting a catalyst component on the introduced substituting elements, a precursor for the Pt is loaded and then sintered in a reducing atmosphere. Using a reducing atmosphere allows the metallization temperature to be as low as about 400° C., thereby reducing thermal vibration and suppressing aggregation in order to achieve an effect of reducing the mean particle size of the catalyst to about 100 nm or smaller.

Abstract: It is an object of the present invention to realize an oxidizing catalyst having weak oxidizing capability such that NO is oxidized to NO2 and HC is not oxidized, and high thermal durability, and to use it as a catalyst in a preceding stage for supplying NO2 and HC stably to a catalyst in the following stage.

Abstract: This invention aims at achieving early activation by use of a catalytic body having a low thermal capacity, and a low pressure loss, without using a coating layer to reduce exhaust emission. The invention is directed also to improve exhaust purification performance by improving the combination of catalytic bodies and performance of each catalytic body. In the invention, a start catalyst 1 is arranged at an upstream portion of an exhaust pipe P of a car engine E and a three way catalyst 2 is disposed on the downstream side. The start catalyst 1 can directly support catalytic components through chemical bonds by incorporating replacing elements into a substrate ceramic having high heat resistance such as cordierite. Because a coating layer is not necessary, the catalyst of the invention has a low heat capacity and a large open area and achieves reduction of exhaust emission, and reduction of a pressure loss, through early activation.

Abstract: There is no conventional method for precisely estimating under what external conditions each partial circuit, such as a library cell, is utilized in an actual integrated circuit at the time of designing the partial circuit. Therefore, by estimating the external conditions of a partial circuit when used in an integrated circuit so that the partial circuit is designed in accordance with the external conditions, the partial circuit having optimal performance for the external conditions can be designed.

Abstract: The present invention has an object to obtain a ceramic body that can support a required amount of catalyst component, without lowering the characteristics such as strength, being manufactured without forming a coating layer and providing a high performance ceramic catalyst body that is excellent in practical utility and durability.

Abstract: The present invention provides a ceramic catalyst body having more excellent catalytic performance using a ceramic carrier capable of directly supporting the catalyst component.

Abstract: The present invention provides a catalyst-loaded ceramic filter that is made of a ceramic material capable of directly supporting a catalyst component thereon, and is capable of providing early activation of the catalyst with a low coefficient of thermal expansion and light weight, without compromising the high porosity of the filter substrate.

Abstract: The present invention provides a hollow ceramic monolithic support that has high isostatic strength, a method of manufacturing the hollow ceramic monolithic support at low cost, and a molding die therefor.

Abstract: Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

Abstract: In designing an integrated circuit, the size of a transistor is optimized together with the folding number thereof. The optimization of the size and folding number of the transistor is accomplished by using a folding model in which a plurality of folding numbers are assumed for one transistor size. In the folding model, if the lower limit value of the transistor size W is W0 and the height of a placement region for the transistor is H0, the folding number N can be determined arbitrarily so long as W/H0≦N≦W/W0 is satisfied. If the size of the transistor is optimized together with the folding number thereof by using the folding model so long as a given design constraint is satisfied, there can be designed an integrated circuit which has been improved in terms of area and performance.

Abstract: The present invention provides a ceramic carrier and a ceramic catalyst which have NOx absorbent capacity, low heat capacity, low pressure loss and high practical value.

Abstract: The present invention realizes the optimization of a transistor size with higher precision and in a shorter time, in designing a layout for an integrated circuit. A diffusion sharing estimation section estimates a diffusion-sharing region in the layout of the integrated circuit based on circuit data. A circuit characteristic evaluation section evaluates the characteristics, such as area, delay and power consumption, of the integrated circuit in accordance with the information about the diffusion-sharing region estimated by the diffusion sharing estimation section. A transistor size optimization section sets various size candidates for each of the transistors, which constitute the integrated circuit, provides these size candidates to the diffusion sharing estimation section and the circuit characteristic evaluation section, and then selects an optimum transistor size from the transistor size candidates thus set in accordance with the evaluation results obtained by the circuit characteristic evaluation section.

Abstract: It is an object of the present invention to provide a ceramic catalyst body with a better catalyst performance by using a ceramic carrier capable of directly supporting a catalyst component.

Abstract: The present invention improves a ceramic carrier capable of directly supporting a catalyst component and provides a ceramic carrier and a ceramic catalyst body which have high catalyst performance and practical value.

Abstract: (i) In a ceramic catalyst body which comprises a ceramic carrier which has a multitude of pores capable of supporting a catalyst directly on the surface of a substrate ceramic and a catalyst supported on the ceramic carrier, a layer containing an anti-evaporation metal such as Rh is formed on the outer surface of catalyst metal particles such as Pt or Rh.

Abstract: The object of the present invention is to improve the catalyst performance of a ceramic support that enables a catalyst component to be loaded directly, prevent thermal degradation and so forth, and enhance durability.

Abstract: A semiconductor device trimming method or apparatus is proposed for use with a semiconductor device which includes at least a regular cell array, a spare cell array, a fuse array, and a spare decoder. In the method or apparatus, a trimming table is prepared which lists all address modes of address signals for row or column address lines to be replaced in the regular cell array and the blow mode of the fuse array corresponding to each of the address modes. Then, fuses are selectively blown in the fuse array according to the blow mode corresponding to row or column lines of which the selection has been inhibited in the regular cell array in accordance with the trimming table. The spare decoder inhibits selection of cells in the regular cell array and permit selection of cells on the spare lines in the spare cell array in order to replace the inhibited row or column lines in the regular cell array.

Abstract: An apparatus and method for generating a laser trimming program without causing errors due to development by human hands in a time that does not depend on experiences etc. of a person who generates a program, as well as a recording medium on which a program for execution of such a method is recorded and a laser trimming apparatus using such a program. Fuse coordinate calculation programs are stored in advance in a coordinate calculation program database on a memory core basis and a common portion of an LT program is stored in advance in a common program database. At the time of generating an LT program, type information of a memory core incorporated in a target IC chip is input and a corresponding fuse coordinate calculation program is selected from the fuse coordinate calculation programs stored in the coordinate calculation program database and then loaded.

Abstract: There is no conventional method for precisely estimating under what external conditions each partial circuit, such as a library cell, is utilized in an actual integrated circuit at the time of designing the partial circuit. Therefore, by estimating the external conditions of a partial circuit when used in an integrated circuit so that the partial circuit is designed in accordance with the external conditions, the partial circuit having optimal performance for the external conditions can be designed.

Abstract: The invention provides a functional module model for realizing optimal pipelining. The functional module model includes division line data representing division lines corresponding to positions where pipeline registers can be inserted and delay/area data representing the trade-off relationship between the delay and the area of each division area partitioned by the division lines. By using this functional module model, a pipeline register insertion position is selected among the division lines represented by the division line data, and the delay and the area of each division area are set on the basis of the trade-off relationship represented by the delay/area data. Thus, a pipelined circuit with a minimized area can be synthesized.