Abstract: A hair dye composition containing an azo dye (1) or a salt thereof, (wherein R1 to R4 represents H, aliphatic hydrocarbon group, aryl group, halogen atom, acyl group, cyano group, acylamino group, or the like, wherein R1 and R2, and/or R3 and R4 may be coupled to form a 5- or 6-membered ring; X represents C or N, with the proviso that when X represents C, n stands for 1, and when X represents N, n stands for 0; A1, A2, A3 and A4 each represents N or represents C substituted by Y or having H, with the proviso that at least one of A1, A2, A3 and A4 is a nitrogen atom; and Y represents a substituent with the proviso that m stands for an integer from 0 to 3).

Abstract: A power semiconductor device has a first base layer of first conductive type, a contact layer of first conductive type formed on a surface of the first base layer, a second base layer of first conductive layer which is formed on the surface of the first base layer at a side opposite to the first contact layer and has an impurity concentration higher than that of the first base layer, a second contact layer of second conductive type formed on the surface of the first base layer or the second base layer, and a junction termination region formed in vicinity of or in contact with outside in a horizontal direction of the second contact layer.

Abstract: A hair dye composition containing an azo dye (1) or a salt thereof, (wherein R1 to R4 represents H, aliphatic hydrocarbon group, aryl group, halogen atom, acyl group, cyano group, acylamino group, or the like, wherein R1 and R2, and/or R3 and R4 may be coupled to form a 5- or 6-membered ring; X represents C or N, with the proviso that when X represents C, n stands for 1, and when X represents N, n stands for 0; A1, A2, A3 and A4 each represents N or represents C substituted by Y or having H, with the proviso that at least one of A1, A2, A3 and A4 is a nitrogen atom; and Y represents a substituent with the proviso that m stands for an integer from 0 to 3).

Abstract: A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are e

Abstract: A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and t

Abstract: A hair dye composition containing an azo dye (1) or a salt thereof: wherein R represents a coupler moiety, R1 and R3 each independently represent —SO3M, —SO2NR4R5 or a hydrogen atom, R2, R4 and R5 each independently represent a hydrogen atom or a substituent, and M represents a hydrogen atom, metal atom or ammonium, with a proviso that R1 and R3 are not hydrogen atoms at the same time.

Abstract: This disclosure concerns a semiconductor device that includes a first base layer; second base layers provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers; an emitter layer formed on a surface of the second base layers; a collector layer provided below a second surface of the first base layer, an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being electrically isolated from the emitter layer and the second base layers, wherein the space section includes a semiconductor layer being deeper than the second base layers.

Abstract: A hair dye composition containing an azo dye (1) or a salt thereof wherein R represents a coupler moiety, R1 and R3 each independently represent —SO3M, —SO2NR4R5 or a hydrogen atom, R2, R4 and R5 each independently represent a hydrogen atom or a substituent, and M represents a hydrogen atom, metal atom or ammonium, with a proviso that R1 and R3 are not hydrogen atoms at the same time.

Abstract: Disclosed is a power semiconductor device, including: a gate electrode having a cross section having a length in a vertical direction, and having a shape extending in a direction orthogonal to the cross section; a gate insulating film surrounding the gate electrode; an n-type source layer positioning to face the gate electrode via the gate insulating film; a p-type base layer adjacent to the n-type source layer and positioning to face the gate electrode via the gate insulating film; an n-type base layer adjacent to the p-type base layer and positioning to face the gate electrode via the gate insulating film without being in contact with the n-type source layer; and a main electrode being in contact with the n-type source layer and the p-type base layer with plural lateral planes extending in a direction crossing the direction in which the gate electrode is extending.

Abstract: This semiconductor device comprises a drift layer of a first conductivity type formed on a drain layer of a first conductivity type, and a drain electrode electrically connected to the drain layer. A semiconductor base layer of a second conductivity type is formed in a surface of the drift layer, and a source region of a first conductivity type is further formed in the semiconductor base layer. A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes is 0.3 micrometers or less.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.

Abstract: A semiconductor device comprises a drain layer of first conductivity type, drift layers of first and second conductivity types on the drain layer, an insulating film between the drift layers and contacting the drift layers, a first base layer of second conductivity type on a surface of the drift layer of first conductivity type, a source layer of first conductivity type selectively provided on a surface of the first base layer of second conductivity type, a gate insulating film on the first base layer of second conductivity type between the source layer and the drift layer, a gate electrode on the gate insulating film, a second base layer of second conductivity type on a surface of the drift layer, a first main electrode on the drain layer, and a second main electrode on the source layer, the first base layer and the second base layer.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: Disclosed is a power semiconductor device, including: a gate electrode having a cross section having a length in a vertical direction, and having a shape extending in a direction orthogonal to the cross section; a gate insulating film surrounding the gate electrode; an n-type source layer positioning to face the gate electrode via the gate insulating film; a p-type base layer adjacent to the n-type source layer and positioning to face the gate electrode via the gate insulating film; an n-type base layer adjacent to the p-type base layer and positioning to face the gate electrode via the gate insulating film without being in contact with the n-type source layer; and a main electrode being in contact with the n-type source layer and the p-type base layer with plural lateral planes extending in a direction crossing the direction in which the gate electrode is extending.

Abstract: A power semiconductor device has a first base layer of first conductive type, a contact layer of first conductive type formed on a surface of the first base layer, a second base layer of first conductive layer which is formed on the surface of the first base layer at a side opposite to the first contact layer and has an impurity concentration higher than that of the first base layer, a second contact layer of second conductive type formed on the surface of the first base layer or the second base layer, and a junction termination region formed in vicinity of or in contact with outside in a horizontal direction of the second contact layer.

Abstract: A power semiconductor device according to the present invention comprises: a first conductive type base layer; a second conductive type base layer selectively formed on the first conductive type base layer; an insulation layer formed in the region on the first conductive type base layer on which the second conductive type base layer is not formed; a gate insulation film formed on the inner surface of a trench formed between the second conductive type base layer and the insulation layer so as to separate them from each other and to reach the first conductive type base layer from the surface of the second conductive type base layer; a first conductive type source layer selectively formed on the surface of the second conductive type base layer in contact with the gate insulation film; a gate electrode formed in the trench and insulated from the first conductive type base layer, the second conductive type base layer, and the first conductive type source layer by the gate insulation film; a main electrode electric

Abstract: A method of manufacturing a semiconductor device in which a trench groove is formed in a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer is epitaxially grown so as to bury the trench groove. The second conductivity type semiconductor layer is then removed until a surface of the first conductivity type semiconductor layer is exposed. The first conductivity type semiconductor layer is epitaxially grown on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove.

Abstract: A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are e