Patents by Inventor Masakazu Yamaguchi
Masakazu Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7078740Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.Type: GrantFiled: May 12, 2004Date of Patent: July 18, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Masakazu Yamaguchi, Hideaki Ninomiya, Ichiro Omura, Tomoki Inoue
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Patent number: 7075168Abstract: A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are eType: GrantFiled: December 21, 2004Date of Patent: July 11, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Sugiyama, Tomoki Inoue, Hideaki Ninomiya, Masakazu Yamaguchi
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Publication number: 20060145290Abstract: A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.Type: ApplicationFiled: December 6, 2005Publication date: July 6, 2006Inventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Akihiko Osawa, Wataru Saito, Masakazu Yamaguchi, Ichiro Omura
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Patent number: 6995426Abstract: A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.Type: GrantFiled: December 26, 2002Date of Patent: February 7, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Akihiko Osawa, Wataru Saito, Masakazu Yamaguchi, Ichiro Omura
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Publication number: 20060006409Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.Type: ApplicationFiled: September 9, 2005Publication date: January 12, 2006Inventors: Masakazu Yamaguchi, Hideaki Ninomiya, Ichiro Omura, Tomoki Inoue
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Publication number: 20050263852Abstract: A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and tType: ApplicationFiled: October 28, 2004Publication date: December 1, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo Ogura, Masakazu Yamaguchi, Tomoki Inoue, Hideaki Ninomiya, Koichi Sugiyama
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Patent number: 6936893Abstract: The power semiconductor device includes a plurality of trenches disposed in a surface of a semiconductor active layer to reach a first base layer of a first conductivity type. The trenches are disposed at intervals to partition a main cell and a dummy cell. In the main cell, a second base layer of a second conductivity type and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode and gate insulating film are disposed in each trench. A partition structure is disposed in the surface of the semiconductor active layer to electrically isolate the buffer layer from the emitter electrode.Type: GrantFiled: October 3, 2003Date of Patent: August 30, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Tanaka, Shinichi Umekawa, Tadashi Matsuda, Masakazu Yamaguchi
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Publication number: 20050161768Abstract: A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are eType: ApplicationFiled: December 21, 2004Publication date: July 28, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi Sugiyama, Tomoki Inoue, Hideaki Ninomiya, Masakazu Yamaguchi
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Patent number: 6921687Abstract: In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type base layer, the point of the highest impurity concentration is located closer to the n-type base layer than the junction with the emitter layer. In other words, the pinch-off of the channel is generated in the position closer to the n-type base layer than to the junction between the p-type base layer and the n-type emitter layer.Type: GrantFiled: October 13, 2004Date of Patent: July 26, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hidetaka Hattori, Masakazu Yamaguchi
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Patent number: 6894347Abstract: A semiconductor element including a first base layer of a first conductivity type; a second base layer of a second conductivity type formed selectively in one surface region of the first base layer; an emitter layer or a source layer of the first conductivity type formed selectively in a surface region of the second base layer; and a gate electrode formed on that portion of the second base layer which is positioned between the emitter layer or source layer and the first base layer with a gate insulating film interposed between the gate electrode and the second base layer. A channel region is formed in contact with the gate insulating film to permit a carrier to migrate between the emitter layer or source layer and the first base layer. The channel region has an impurity concentration profile such that the impurity concentration is substantially constant along the gate insulating film and in the direction in which the emitter layer or source layer, the second base layer and the first base layer are formed.Type: GrantFiled: October 30, 2003Date of Patent: May 17, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hidetaka Hattori, Masakazu Yamaguchi
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Publication number: 20050098826Abstract: A method of manufacturing a semiconductor device in which a trench groove is formed in a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer is epitaxially grown so as to bury the trench groove. The second conductivity type semiconductor layer is then removed until a surface of the first conductivity type semiconductor layer is exposed. The first conductivity type semiconductor layer is epitaxially grown on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove.Type: ApplicationFiled: December 3, 2004Publication date: May 12, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Masakazu Yamaguchi, Wataru Saito, Ichiro Omura, Masaru Izumisawa
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Publication number: 20050062064Abstract: In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type base layer, the point of the highest impurity concentration is located closer to the n-type base layer than the junction with the emitter layer. In other words, the pinch-off of the channel is generated in the position closer to the n-type base layer than to the junction between the p-type base layer and the n-type emitter layer.Type: ApplicationFiled: October 13, 2004Publication date: March 24, 2005Inventors: Hidetaka Hattori, Masakazu Yamaguchi
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Patent number: 6844592Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer which includes a cell region portion and a junction terminating region portion. The junction terminating region portion is a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field.Type: GrantFiled: March 17, 2003Date of Patent: January 18, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Masakazu Yamaguchi, Wataru Saito, Ichiro Omura, Masaru Izumisawa
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Publication number: 20040238884Abstract: The power semiconductor device includes a plurality of trenches disposed in a surface of a semiconductor active layer to reach a first base layer of a first conductivity type. The trenches are disposed at intervals to partition a main cell and a dummy cell. In the main cell, a second base layer of a second conductivity type and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode and gate insulating film are disposed in each trench. A partition structure is disposed in the surface of the semiconductor active layer to electrically isolate the buffer layer from the emitter electrode.Type: ApplicationFiled: October 3, 2003Publication date: December 2, 2004Inventors: Masahiro Tanaka, Shinichi Umekawa, Tadashi Matsuda, Masakazu Yamaguchi
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Patent number: 6809349Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.Type: GrantFiled: January 30, 2003Date of Patent: October 26, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Masakazu Yamaguchi, Hideaki Ninomiya, Ichiro Omura, Tomoki Inoue
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Publication number: 20040207009Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.Type: ApplicationFiled: May 12, 2004Publication date: October 21, 2004Inventors: Masakazu Yamaguchi, Hideaki Ninomiya, Ichiro Omura, Tomoki Inoue
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Publication number: 20040089886Abstract: In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type base layer, the point of the highest impurity concentration is located closer to the n-type base layer than the junction with the emitter layer. In other words, the pinch-off of the channel is generated in the position closer to the n-type base layer than to the junction between the p-type base layer and the n-type emitter layer.Type: ApplicationFiled: October 30, 2003Publication date: May 13, 2004Inventors: Hidetaka Hattori, Masakazu Yamaguchi
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Publication number: 20040084722Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.Type: ApplicationFiled: January 30, 2003Publication date: May 6, 2004Inventors: Masakazu Yamaguchi, Hideaki Ninomiya, Ichiro Omura, Tomoki Inoue
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Publication number: 20040043565Abstract: A semiconductor device comprises a drain layer of first conductivity type, drift layers of first and second conductivity types on the drain layer, an insulating film between the drift layers and contacting the drift layers, a first base layer of second conductivity type on a surface of the drift layer of first conductivity type, a source layer of first conductivity type selectively provided on a surface of the first base layer of second conductivity type, a gate insulating film on the first base layer of second conductivity type between the source layer and the drift layer, a gate electrode on the gate insulating film, a second base layer of second conductivity type on a surface of the drift layer, a first main electrode on the drain layer, and a second main electrode on the source layer, the first base layer and the second base layer.Type: ApplicationFiled: April 1, 2003Publication date: March 4, 2004Inventors: Masakazu Yamaguchi, Ichiro Omura, Wataru Saito, Takashi Shinohe, Hiromichi Ohashi
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Patent number: 6693338Abstract: A semiconductor device includes a drain layer, first and second drift layers, a RESURF layer, a drain electrode, a base layer, a source layer, a source electrode, and a gate electrode. The first drift layer is formed on the drain layer. The second drift layers and RESURF layers are formed on the first drift layer and periodically arranged in a direction perpendicular to the direction of depth. The RESURF layer forms a depletion layer in the second drift layer by a p-n junction including the second drift layer and RESURF layer. The impurity concentration in the first drift layer is different from that in the second drift layer. The drain electrode is electrically connected to the drain layer.Type: GrantFiled: June 7, 2002Date of Patent: February 17, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saitoh, Ichiro Omura, Masakazu Yamaguchi, Satoshi Aida, Syotaro Ono