Patents by Inventor Masaki Shiraishi
Masaki Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9412701Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: GrantFiled: July 2, 2014Date of Patent: August 9, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
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Publication number: 20160109896Abstract: In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided having a circuit in which a power MOS·FET for a high-side switch and a power MOS·FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS·FET for the high-side switch is formed by a p channel vertical MOS·FET, and the power MOS·FET for the low-side switch is formed by an n channel vertical MOS·FET. Thus, a semiconductor chip formed with the power MOS·FET for the high-side switch and a semiconductor chip formed with the power MOS·FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.Type: ApplicationFiled: December 27, 2012Publication date: April 21, 2016Inventors: Masaki SHIRAISHI, Noboru AKIYAMA, Tomoaki UNO, Nobuyoshi MATSUURA
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Publication number: 20160020309Abstract: The problem addressed by the present invention is to provide a semiconductor device capable of improving dv/dt controllability via a gate drive circuit during turn-on switching. The semiconductor device comprises a plurality of trench gate groups, each trench gate group including mutually adjoining three or more trench gates, and the distance between adjoining two trench gate groups is larger than the distance between adjoining two trench gates in one trench gate group. Thereby, gate-emitter capacity increases, and therefore the semiconductor device may improve dv/dt controllability via a gate drive circuit during turn-on switching.Type: ApplicationFiled: December 3, 2013Publication date: January 21, 2016Inventors: Hiroshi Suzuki, Masaki Shiraishi, So Watanabe, Tetsuya Ishimaru
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Publication number: 20160005854Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: ApplicationFiled: September 17, 2015Publication date: January 7, 2016Inventors: Masaki SHIRAISHI, Tomoaki UNO, Nobuyoshi MATSUURA
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Patent number: 9153686Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: GrantFiled: July 24, 2014Date of Patent: October 6, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masaki Shiraishi, Tomoaki Uno, Nobuyoshi Matsuura
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Patent number: 9082814Abstract: A semiconductor device includes first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type that is formed near a surface of the first semiconductor layer; a first main electrode that is electrically connected to the second semiconductor layer; a third semiconductor layer of the second conductivity type that neighbors the first semiconductor layer; a fourth semiconductor layer of the first conductivity type that is selectively disposed in an upper portion of the third semiconductor layer; a second main electrode that is electrically connected to the third semiconductor layer and the fourth semiconductor layer; a trench whose side face is in contact with the third semiconductor layer and the fourth semiconductor layer; a gate electrode that is formed along the side face of the trench by a sidewall of polysilicon; and a polysilicon electrode.Type: GrantFiled: January 11, 2012Date of Patent: July 14, 2015Assignee: Hitachi Power Semiconductor Device, Ltd.Inventors: Masaki Shiraishi, Mutsuhiro Mori, Hiroshi Suzuki, So Watanabe
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Publication number: 20140332878Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: ApplicationFiled: July 24, 2014Publication date: November 13, 2014Inventors: Masaki SHIRAISHI, Tomoaki UNO, Nobuyoshi MATSUURA
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Publication number: 20140312510Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: ApplicationFiled: July 2, 2014Publication date: October 23, 2014Inventors: Yukihiro SATOU, Tomoaki UNO, Nobuyoshi MATSUURA, Masaki SHIRAISHI
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Patent number: 8853846Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: GrantFiled: November 5, 2013Date of Patent: October 7, 2014Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Tomoaki Uno, Nobuyoshi Matsuura
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Patent number: 8796827Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: GrantFiled: August 29, 2013Date of Patent: August 5, 2014Assignee: Renesas Electronics CorporationInventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
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Publication number: 20140054692Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: ApplicationFiled: November 5, 2013Publication date: February 27, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masaki SHIRAISHI, Tomoaki UNO, Nobuyoshi MATSUURA
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Patent number: 8653588Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on the first semiconductor layer; trenches in the first semiconductor layer; a semiconductor protruding part on the first semiconductor layer; a third semiconductor layer on the semiconductor protruding part; a fourth semiconductor layer on the third semiconductor layer; a gate insulating layer disposed along the trench; a first interlayer insulating layer disposed along the trench; a first conductive layer facing to the fourth semiconductor layer; a second conductive layer on the first interlayer insulating layer; a second interlayer insulating layer covering the second conductive layer; a third conductive layer on the third semiconductor layer and fourth semiconductor layer; a contacting part connecting the third conductive layer and third semiconductor layer; and a fourth conductive layer formed on the second semiconductor layer.Type: GrantFiled: July 19, 2012Date of Patent: February 18, 2014Assignee: Hitachi, Ltd.Inventors: So Watanabe, Masaki Shiraishi, Hiroshi Suzuki, Mutsuhiro Mori
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Patent number: 8653606Abstract: It is intended to provide a semiconductor device capable to improve a controllability of dv/dt by a gate drive circuit during a turn-on switching period, while maintaining a low loss and a high breakdown voltage. Trench gates are disposed so as to have narrow distance regions and wide distance regions, wherein each of the narrow distance regions is provided with a channel region, and each of the wide distance regions is provided with trenches, each trench having an electrode electrically connected to the emitter electrode. In this manner, even if a floating-p layer is removed, it is possible to reduce a feedback capacity and maintain a breakdown voltage.Type: GrantFiled: June 27, 2013Date of Patent: February 18, 2014Assignee: Hitachi, Ltd.Inventor: Masaki Shiraishi
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Patent number: 8638577Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.Type: GrantFiled: September 13, 2011Date of Patent: January 28, 2014Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Takayuki Hashimoto, Noboru Akiyama
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Publication number: 20140003002Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: ApplicationFiled: August 29, 2013Publication date: January 2, 2014Applicant: Renesas Electronics CorporationInventors: Yukihiro SATOU, Tomoaki UNO, Nobuyoshi MATSUURA, Masaki SHIRAISHI
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Publication number: 20140003109Abstract: It is intended to provide a semiconductor device capable to improve a controllability of dv/dt by a gate drive circuit during a turn-on switching period, while maintaining a low loss and a high breakdown voltage. Trench gates are disposed so as to have narrow distance regions and wide distance regions, wherein each of the narrow distance regions is provided with a channel region, and each of the wide distance regions is provided with trenches, each trench having an electrode electrically connected to the emitter electrode. In this manner, even if a floating-p layer is removed, it is possible to reduce a feedback capacity and maintain a breakdown voltage.Type: ApplicationFiled: June 27, 2013Publication date: January 2, 2014Inventor: Masaki SHIRAISHI
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Patent number: 8592904Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: GrantFiled: August 17, 2012Date of Patent: November 26, 2013Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Tomoaki Uno, Nobuyoshi Matsuura
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Patent number: 8575733Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: GrantFiled: December 17, 2012Date of Patent: November 5, 2013Assignee: Renesas Electronics CorporationInventors: Yohihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
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Patent number: 8519533Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.Type: GrantFiled: February 14, 2012Date of Patent: August 27, 2013Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Tomoaki Uno, Nobuyoshi Matsuura
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Patent number: 8482345Abstract: A non-insulated DC-DC converter has a power MOS•FET for a highside switch and a power MOS•FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS•FET for the highside switch and the power MOS•FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS•FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.Type: GrantFiled: November 10, 2011Date of Patent: July 9, 2013Assignee: Renesas Electronics CorporationInventors: Tomoaki Uno, Masaki Shiraishi, Nobuyoshi Matsuura, Toshio Nagasawa