Patents by Inventor Masaki Shiraishi

Masaki Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090207640
    Abstract: The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS*FET for a high-side switch and a power MOS*FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS*FET for the high-side switch is formed by a p channel vertical MOS*FET, and the power MOS*FET for the low-side switch is formed by an n channel vertical MOS*FET. Thus, a semiconductor chip formed with the power MOS*FET for the high-side switch and a semiconductor chip formed with the power MOS*FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
    Type: Application
    Filed: April 28, 2009
    Publication date: August 20, 2009
    Inventors: Masaki Shiraishi, Noboru Akiyama, Tomoaki Uno, Nobuyoshi Matsuura
  • Publication number: 20090179235
    Abstract: A semiconductor device in which the self-turn-on phenomenon is prevented that can significantly improve power conversion efficiency. The semiconductor device is a system-in-package for power supply applications in which a high-side switch, a low-side switch, and two drivers are included in a single package. The device includes an auxiliary switch disposed between the gate and source of said low-side switch, and a low-side MOSFET 3 for the low-side switch and an auxiliary MOSFET 4 for the auxiliary switch are disposed on the same chip. In this way, the self-turn-on phenomenon can be prevented, allowing the mounting of a low-side MOSFET 3 with a low threshold voltage and thereby significantly improving power conversion efficiency. The gate of the auxiliary MOSFET 4 is driven by the driver for the high-side MOSFET 2, thereby eliminating the need for a new drive circuit and realizing the same pin configuration as existing products, which facilitates easy replacement.
    Type: Application
    Filed: March 17, 2009
    Publication date: July 16, 2009
    Inventors: Masaki Shiraishi, Takayuki Iwasaki, Nobuyoshi Matsuura
  • Patent number: 7554181
    Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: June 30, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
  • Patent number: 7554209
    Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: June 30, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
  • Publication number: 20090154209
    Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.
    Type: Application
    Filed: January 6, 2009
    Publication date: June 18, 2009
    Inventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
  • Patent number: 7535741
    Abstract: The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: May 19, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masaki Shiraishi, Noboru Akiyama, Tomoaki Uno, Nobuyoshi Matsuura
  • Patent number: 7514731
    Abstract: A semiconductor device in which the self-turn-on phenomenon is prevented that can significantly improve power conversion efficiency. The semiconductor device is a system-in-package for power supply applications in which a high-side switch, a low-side switch, and two drivers are included in a single package. The device includes an auxiliary switch disposed between the gate and source of said low-side switch, and a low-side MOSFET 3 for the low-side switch and an auxiliary MOSFET 4 for the auxiliary switch are disposed on the same chip. In this way, the self-turn-on phenomenon can be prevented, allowing the mounting of a low-side MOSFET 3 with a low threshold voltage and thereby significantly improving power conversion efficiency. The gate of the auxiliary MOSFET 4 is driven by the driver for the high-side MOSFET 2, thereby eliminating the need for a new drive circuit and realizing the same pin configuration as existing products, which facilitates easy replacement.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: April 7, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masaki Shiraishi, Takayuki Iwasaki, Nobuyoshi Matsuura
  • Publication number: 20090039394
    Abstract: The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package.
    Type: Application
    Filed: October 8, 2008
    Publication date: February 12, 2009
    Inventors: Tomoaki UNO, Masaki Shiraishi, Nobuyoshi Matsuura, Yukihiro Satou
  • Publication number: 20090033377
    Abstract: A drive circuit for driving a semiconductor element is equipped with: a first switch connected to a positive side of a DC power supply; a second switch connected to the other terminal of the first switch and to a negative side of the DC power supply; a third switch connected to the positive side of the DC power supply; a fourth switch connected to the other terminal of the third switch; a fifth switch connected to the other terminal of the fourth switch and to the negative side of the DC power supply; and a capacitor connected to the other terminal of the first switch and to the other terminal of the fourth switch. A gate of the semiconductor element is connected to the other terminal of said third switch; and a source of the semiconductor element is connected to the negative side of the DC power supply.
    Type: Application
    Filed: July 10, 2008
    Publication date: February 5, 2009
    Inventors: Takayuki Hashimoto, Takashi Hirao, Masaki Shiraishi
  • Publication number: 20090026830
    Abstract: An elastic wheel comprises a rim for mounting a tire, a disk to be fixed to an axle, and a connecting apparatus for connecting elastically between the rim and disk, the apparatus comprising a pair of axially spaced internal flanges each provided on an inner circumference side of the rim and extending circumferentially, an external flange provided on a radially outer portion of the disk, the external flange disposed in a space between the internal flanges with an axial gap on its both sides and extending circumferentially, a pair of rubber dampers each disposed in the axial gap and connecting between the internal and external flanges, wherein each internal flange is provided on its axially inner side with a first groove, the external flange is provided on its both sides with a second groove so as to face each first groove, axial ends of each damper are inserted into the first and second grooves, and a radial gap is provided between the external flange and the inner circumference side of the rim in the space.
    Type: Application
    Filed: June 1, 2005
    Publication date: January 29, 2009
    Inventors: Masaki Shiraishi, Tadashi Imamura, Yoshiaki Kimura, Kenji Maki
  • Publication number: 20090026544
    Abstract: A non-insulated DC-DC converter has a power MOS•FET for a highside switch and a power MOS•FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS•FET for the highside switch and the power MOS•FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS•FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.
    Type: Application
    Filed: September 24, 2008
    Publication date: January 29, 2009
    Inventors: Tomoaki Uno, Masaki Shiraishi, Nobuyoshi Matsuura, Toshio Nagasawa
  • Patent number: 7480163
    Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: January 20, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
  • Publication number: 20090015224
    Abstract: A DC-DC converter that prevents self turn-on and improves the power efficiency is provided. In a non-insulated DC-DC converter, self turn-on is prevented by applying a negative voltage between a gate and a source of a low side MOSFET by the use of a capacitor for generating negative voltage when the low side MOSFET is in an OFF state. Also, when the low side MOSFET is in an ON state due to the capacitor for generating negative voltage, a positive voltage applied between the gate and the source of the low side MOSFET does not drop from a voltage of a gate driving DC power source that is supplied from a gate power input terminal. Therefore, the power efficiency is improved.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 15, 2009
    Inventors: Takashi Hirao, Takayuki Hashimoto, Masaki Shiraishi
  • Publication number: 20080315257
    Abstract: In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode electrode of the diode is electrically connected to an anode region via a conductive material embedded in a via hole (hole) reaching a p+ region which is the anode region of the main surface of the semiconductor substrate from a main surface of the compound semiconductor layer.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 25, 2008
    Inventor: Masaki SHIRAISHI
  • Patent number: 7436070
    Abstract: A non-insulated DC-DC converter hs a power MOS•FRT for a highside switch and a power MOS•FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS•FET for the highside switch and the power MOS•FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS•FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: October 14, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Tomoaki Uno, Masaki Shiraishi, Nobuyoshi Matsuura, Toshio Nagasawa
  • Patent number: 7434456
    Abstract: A method for pneumatic tire simulation comprises the steps of modeling a tire body having a cavity extending in a circumferential direction of the tire using finite elements to build a tire body model, modeling the cavity surrounded by the tire body using finite volumes to build a cavity model, setting a pneumatic tire model coupled the tire body model with the cavity model so that a relative distance between an outer surface of the cavity model and an inner surface of the tire body model does not change, modeling a road using finite elements to build a road model, and executing a numerical simulation in which the tire model is made to roll on the road model in a predetermined condition.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: October 14, 2008
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventor: Masaki Shiraishi
  • Publication number: 20080217684
    Abstract: A semiconductor device comprises a trench-gate type field-effect transistor on a semiconductor substrate having a first main surface and a second main surface oppositely positioned in a thickness direction, wherein the trench-gate type field-effect transistor comprises a first semiconductor region at the first main surface side; a second semiconductor region at the second main surface; a semiconductor well region between the first semiconductor region and the second semiconductor region; a trench formed so as to protrude in a first direction intersecting the second main surface; a gate electrode formed on an inner surface of the trench via a gate insulating film, and a bottom of the gate electrode is in the first semiconductor region, and a well bottom has a well deep portion and a well shallow portion, and the well deep portion is in a region more distant from the gate insulating film compared to the well shallow portion.
    Type: Application
    Filed: January 25, 2008
    Publication date: September 11, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Takayuki Hashimoto, Takashi Hirao, Masaki Shiraishi
  • Patent number: 7415871
    Abstract: A method of simulating rolling tire comprises the steps of: modeling the tire in finite elements to make a tire model which comprises a first element having a viscoelastic property; modeling a road in finite elements to make a road model; executing a numerical simulation in which the tire model is made to roll on the road model at a predetermined condition; obtaining six kinds of strains in time sequence from the first element of the tire model with rolling, the six kinds of strains including three kinds of normal strains along a tire meridian direction, a tire circumferential direction and a tire thickness direction, and three kinds of shear strain along the tire meridian direction, the tire circumferential direction and the tire thickness direction; and calculating energy loss of the first element based on the six kinds of the strains.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: August 26, 2008
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventor: Masaki Shiraishi
  • Patent number: 7418362
    Abstract: A method and device for determining force exerted on a rolling vehicle wheel. Firstly, data on a relationship between a force exerted on a vehicle wheel and a physical parameter such as strain of the radius part of the wheel at predetermined measuring positions are obtained. Using the obtained data on the relationship, a formula for the force is made. Then, the vehicle wheel is measured for the physical parameter during rolling, and using the measured physical parameter and formula, the force is calculated. The force may be a vertical force, lateral force, longitudinal force or self aligning torque. The physical parameter may be the magnitude of a radial strain.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: August 26, 2008
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventor: Masaki Shiraishi
  • Patent number: 7415398
    Abstract: The present invention relates to a method of simulating the deformation of a viscoelastic material in which filler is blended to a matrix made of rubber or resin, the method including the steps of dividing the viscoelastic material into a finite number of elements to form a viscoelastic material model, a step of performing deformation calculation of the viscoelastic material model based on a predetermined condition, and a step of acquiring a necessary physical amount from the deformation calculation, where the step of dividing the viscoelastic material into a finite number of elements includes a step of dividing at least one filler into a finite number of elements to form a filler model, and a step of dividing the matrix into a finite number of elements to form a matrix model.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: August 19, 2008
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventors: Masato Naito, Masaki Shiraishi