Patents by Inventor Masaki Shiraishi
Masaki Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20120049290Abstract: In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.Type: ApplicationFiled: November 10, 2011Publication date: March 1, 2012Inventors: Masaki SHIRAISHI, Noboru AKIYAMA, Tomoaki UNO, Nobuyoshi MATSUURA
-
Publication number: 20120014155Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Inventors: Takayuki HASHIMOTO, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
-
Publication number: 20120001609Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.Type: ApplicationFiled: September 13, 2011Publication date: January 5, 2012Inventors: Masaki SHIRAISHI, Takayuki Hashimoto, Noboru Akiyama
-
Patent number: 8076767Abstract: A non-insulated DC-DC converter has a power MOS-FET for a highside switch and a power MOS-FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS-FET for the highside switch and the power MOS-FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS-FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.Type: GrantFiled: October 26, 2010Date of Patent: December 13, 2011Assignee: Renesas Electronics CorporationInventors: Tomoaki Uno, Masaki Shiraishi, Nobuyoshi Matsuura, Toshio Nagasawa
-
Patent number: 8067979Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.Type: GrantFiled: August 6, 2010Date of Patent: November 29, 2011Assignee: Renesas Electronics CorporationInventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
-
Patent number: 8064235Abstract: In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided including a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p-channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.Type: GrantFiled: October 27, 2010Date of Patent: November 22, 2011Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Noboru Akiyama, Tomoaki Uno, Nobuyoshi Matsuura
-
Publication number: 20110278655Abstract: Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.Type: ApplicationFiled: July 28, 2011Publication date: November 17, 2011Applicant: Renesas Electronics CorporationInventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
-
Publication number: 20110273154Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS·FET for a high side switch and a power MOS·FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: ApplicationFiled: July 22, 2011Publication date: November 10, 2011Inventors: Yukihiro SATOU, Tomoaki UNO, Nobuyoshi MATSUURA, Masaki SHIRAISHI
-
Patent number: 8049479Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.Type: GrantFiled: June 18, 2010Date of Patent: November 1, 2011Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Takayuki Hashimoto, Noboru Akiyama
-
Patent number: 8044520Abstract: A power supply capable of reducing loss of large current and high frequency. In an MCM for power supply in which a high-side power MOSFET chip, a low-side power MOSFET chip and a driver IC chip driving them are sealed in one sealing material (a capsulating insulation resin), a wiring length of a wiring DL connecting an output terminal of the driver IC chip to a gate terminal of the low-side power MOSFET chip or a source terminal is made shorter than a wiring length of a wiring DH connecting the output terminal of the driver IC chip to a gate terminal of the high-side power MOSFET chip or a source terminal. Further, the number of the wiring DL is made larger than the number of the wiring DH.Type: GrantFiled: January 19, 2007Date of Patent: October 25, 2011Assignee: Renesas Electronics CorporationInventors: Noboru Akiyama, Takayuki Hashimoto, Masaki Shiraishi, Tetsuya Kawashima, Koji Tateno, Nobuyoshi Matsuura
-
Patent number: 8044468Abstract: The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package.Type: GrantFiled: October 8, 2008Date of Patent: October 25, 2011Assignee: Renesas Electronics CorporationInventors: Tomoaki Uno, Masaki Shiraishi, Nobuyoshi Matsuura, Yukihiro Satou
-
Publication number: 20110233664Abstract: A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 ?m or less, a p? type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p?type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.Type: ApplicationFiled: June 9, 2011Publication date: September 29, 2011Inventors: Masaki Shiraishi, Yoshito Nakazawa
-
Publication number: 20110227169Abstract: The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package.Type: ApplicationFiled: June 2, 2011Publication date: September 22, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tomoaki UNO, Masaki SHIRAISHI, Nobuyoshi MATSUURA, Yukihiro SATOU
-
Patent number: 8018255Abstract: A DC-DC converter in which self turn-on can be prevented and can improve power efficiency. In a non-insulated DC-DC converter, self turn-on is prevented by applying a negative voltage between a gate and a source of a low side MOSFET by the use of a capacitor for generating negative voltage when the low side MOSFET is in an OFF state. Also, when the low side MOSFET is in an ON state due to the capacitor for generating negative voltage, a positive voltage applied between the gate and the source of the low side MOSFET does not drop from a voltage of a gate driving DC power source that is supplied from a gate power input terminal. Therefore, the power efficiency is improved.Type: GrantFiled: July 11, 2008Date of Patent: September 13, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Hirao, Takayuki Hashimoto, Masaki Shiraishi
-
Patent number: 8013430Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS·FET for a high side switch and a power MOS·FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: GrantFiled: February 18, 2010Date of Patent: September 6, 2011Assignee: Renesas Electronics CorporationInventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
-
Patent number: 8008699Abstract: Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.Type: GrantFiled: March 10, 2010Date of Patent: August 30, 2011Assignee: Renesas Electronics CorporationInventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
-
Patent number: 7981747Abstract: A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 ?m or less, a p?type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p?type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.Type: GrantFiled: April 27, 2009Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Masaki Shiraishi, Yoshito Nakazawa
-
Patent number: 7928589Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: GrantFiled: May 12, 2009Date of Patent: April 19, 2011Assignee: Renesas Electronics CorporationInventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
-
Patent number: 7908128Abstract: Modeling a tire model used for a computer simulation of a pneumatic tire with a toroidal main body and a tread pattern by setting a three-dimensional main body model by dividing the main body by an integer M not less than 2 equally in a circumferential direction of the tire using a finite number of elements, setting a three-dimensional pattern model by dividing the tread pattern by an integer M greater than N equally in the circumferential direction of the tire using a finite number of elements, coupling the pattern model with the main body model while aligning each tire rotation axis to make a three-dimensional tire model, and correcting by moving nodal points existing on a radially outer surface of the pattern model such that a thickness of the pattern model measured from a radially outer surface of the main body model in a normal direction becomes constant.Type: GrantFiled: November 6, 2007Date of Patent: March 15, 2011Assignee: Sumitomo Rubber Industries, Ltd.Inventor: Masaki Shiraishi
-
Publication number: 20110037449Abstract: A non-insulated DC-DC converter has a power MOS-FET for a highside switch and a power MOS-FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS-FET for the highside switch and the power MOS-FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS-FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.Type: ApplicationFiled: October 26, 2010Publication date: February 17, 2011Inventors: Tomoaki UNO, Masaki Shiraishi, Nobuyoshi Matsuura, Toshio Nagasawa