Patents by Inventor Masaki Tamaru

Masaki Tamaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10741545
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: August 11, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Masaki Tamaru, Kazuma Yoshida, Michiya Otsuji, Tetsuyuki Fukushima
  • Patent number: 10593702
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 17, 2020
    Assignee: Socionext Inc.
    Inventors: Masaki Tamaru, Kazuyuki Nakanishi, Hidetoshi Nishimura
  • Publication number: 20200035669
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.
    Type: Application
    Filed: October 2, 2019
    Publication date: January 30, 2020
    Inventors: Masaki TAMARU, Kazuma YOSHIDA, Michiya OTSUJI, Tetsuyuki FUKUSHIMA
  • Patent number: 10403644
    Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: September 3, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Masaki Tamaru
  • Patent number: 10378375
    Abstract: In one embodiment, a power generation planning support apparatus includes an acquiring module configured to acquire a physical quantity that represents a startup condition of a turbine. The apparatus further includes a first storage module configured to store first information that represents a relationship between a startup schedule of the turbine and the physical quantity. The apparatus further includes a predicting module configured to predict the startup schedule of the turbine, based on the physical quantity acquired by the acquiring module and the first information stored in the first storage module. The apparatus further includes an outputting module configured to output the startup schedule predicted by the predicting module.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: August 13, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa Takeuchi, Makoto Takahashi, Yoji Kubo, Masaki Katsumata, Toyohiro Akebi, Masaru Dejima, Keiko Shimizu, Dai Murayama, Shingo Tamaru
  • Publication number: 20180366490
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Inventors: Masaki TAMARU, Kazuyuki NAKANISHI, Hidetoshi NISHIMURA
  • Patent number: 10083985
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: September 25, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Masaki Tamaru, Kazuyuki Nakanishi, Hidetoshi Nishimura
  • Publication number: 20180053783
    Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
    Type: Application
    Filed: October 27, 2017
    Publication date: February 22, 2018
    Inventor: Masaki TAMARU
  • Patent number: 9831271
    Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: November 28, 2017
    Assignee: SOCIONEXT INC.
    Inventor: Masaki Tamaru
  • Publication number: 20170317101
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Masaki TAMARU, Kazuyuki NAKANISHI, Hidetoshi NISHIMURA
  • Patent number: 9741740
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 22, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Masaki Tamaru, Kazuyuki Nakanishi, Hidetoshi Nishimura
  • Publication number: 20160322383
    Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Inventor: Masaki TAMARU
  • Publication number: 20160247820
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Application
    Filed: May 5, 2016
    Publication date: August 25, 2016
    Inventors: Masaki TAMARU, Kazuyuki NAKANISHI, Hidetoshi NISHIMURA
  • Patent number: 9412757
    Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: August 9, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Masaki Tamaru
  • Patent number: 9362264
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 7, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Masaki Tamaru, Kazuyuki Nakanishi, Hidetoshi Nishimura
  • Patent number: 9343461
    Abstract: A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: May 17, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Hiroyuki Shimbo, Masaki Tamaru
  • Publication number: 20150303216
    Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
    Type: Application
    Filed: June 29, 2015
    Publication date: October 22, 2015
    Inventor: Masaki TAMARU
  • Patent number: 9147652
    Abstract: In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: September 29, 2015
    Assignee: SOCIONEXT INC.
    Inventors: Nana Okamoto, Masaki Tamaru, Hidetoshi Nishimura
  • Patent number: 9142539
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: September 22, 2015
    Assignee: SOCIONEXT INC.
    Inventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 9099447
    Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: August 4, 2015
    Assignee: SOCIONEXT INC.
    Inventor: Masaki Tamaru