Abstract: Effective pixels and a failure detection pixel are connected to a control signal line for controlling an operation of the pixels and to an output signal line for outputting a result of failure detection in the pixels. Among the effective pixels, the effective pixels in a same row are connected in common to a same control signal line, and the effective pixels in a same column are connected in common to a same output signal line. The failure detection pixel is connected in common to at least one of the control signal line or the output signal line and configured to detect a failure in any of the effective pixels connected to the at least one of the control signal line or the output signal line.

Abstract: A substrate current suppression circuit includes: a fixed voltage line that supplies a fixed voltage to the collectors of the third and fourth transistors. The fixed voltage is a voltage higher than the base voltage of the third and fourth transistors when the first polarity is p type, and is a voltage lower than the base voltage when the first polarity is n type.

Abstract: A solid-state imaging apparatus includes a plurality of pixel circuits arranged in a matrix. Each pixel circuit includes: a photodiode; a first charge storage that stores a charge; a floating diffusion region that stores a charge; a second charge storage that stores a charge; a first transfer transistor that transfers a charge from the photodiode to the first charge storage; a second transfer transistor that transfers a charge from the first charge storage to the floating diffusion region; a first reset transistor that resets the floating diffusion region; and an accumulating transistor for accumulating a charge of the floating diffusion region in the second charge storage. The capacitance of the first charge storage is greater than the capacitance of the floating diffusion region, and the capacitance of the second charge storage is greater than the capacitance of the floating diffusion region.

Abstract: A solid-state imaging device includes: pixels; a first sample-and-hold circuit provided per column and generating a first differential voltage that is a difference between a first reset voltage and a first signal voltage output from a first pixel disposed in a corresponding column among the pixels; a second sample-and-hold circuit provided per column and generating a second differential voltage that is a difference between a second reset voltage and a second signal voltage output from a second pixel disposed in the corresponding column among the pixels and different from the first pixel; and an A/D conversion circuit provided per column and converting, into digital signals, a first voltage based on the first differential voltage output from the first sample-and-hold circuit disposed in the corresponding column and a second voltage based on the second differential voltage output from the second sample-and-hold circuit disposed in the corresponding column.

Abstract: A solid-state image sensor includes pixel cells each of which is formed in and above a semiconductor substrate and that are arranged in each of a first direction and a second direction intersecting the first direction to form a two-dimensional array. The pixel cells include a first pixel cell and a second pixel cell arranged in the second direction, and the pixel circuit of the first pixel cell and the pixel circuit of the second pixel cell are adjacent to each other in the second direction between the photodetection portion of the first pixel cell and the photodetection portion of the second pixel cell. Each of the first transistors of the first pixel cell shares a gate electrode with the first transistor of the second pixel cell that has the same function as the first transistor of the first pixel cell.

Abstract: A distance-image obtaining method includes: (A) setting a plurality of distance-divided segments in a depth direction, and (B) obtaining a distance image based on each of the plurality of distance-divided segments set. The obtaining of the distance image includes: obtaining a plurality of distance images by imaging two or more of the plurality of distance-divided segments, to obtain a first distance image group; and obtaining a plurality of distance images by imaging distance-divided segments, among the plurality of distance-divided segments, in a phase different from a phase of the two or more of the plurality of distance-divided segments, to obtain a second distance image group.

Abstract: A plurality of pixel cells are provided on a semiconductor substrate and arranged in a two-dimensional array. At least one of the plurality of pixel cells includes a light receiving part, a pixel circuit, and a second transistor. The light receiving part receives an incident light to generate an electrical charge. The pixel circuit includes first transistors arranged side by side along a first direction and a charge retention part that retains the electrical charge generated by the light receiving part. The pixel circuit outputs a light receiving signal in accordance with the electrical charge generated by the light receiving part. The second transistor connects the charge retention part to a memory part that stores the electrical charge. Seen along a thickness direction of the semiconductor substrate, the second transistor is apart from the first transistors in a second direction orthogonal to the first direction.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.

Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.

Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.