Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring.

Abstract: In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.

Abstract: In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: In end portions of first and second gate patterns aligned in parallel relation to each other, and opposite end portions of third and fourth gate patterns aligned in parallel relation to each other, the end portion of the first gate pattern extends to be positioned closer to the third and fourth gate patterns than the end portion of the second gate pattern is, and the opposite end portion of the fourth gate pattern extends to be positioned closer to the first and second gate patterns than the opposite end portion of the third gate pattern is.

Abstract: A plurality of PMOS transistors are provided on a substrate along an X-axis direction such that a gate length direction of each of the PMOS transistors is parallel to the X-axis direction. A plurality of NMOS transistors are provided on the substrate along the X-axis direction such that a gate length direction of each of the NMOS transistors is parallel to the X-axis direction, and each of the plurality of NMOS transistors is opposed to a corresponding one of the PMOS transistors in the Y-axis direction. Gate lines respectively correspond to the PMOS transistors and the NMOS transistors, and are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines passes through gate areas of the PMOS transistors and NMOS transistors which correspond to each of the gate lines.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.

Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.

Abstract: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.