Patents by Inventor Masaki Tamaru

Masaki Tamaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150137248
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Application
    Filed: December 17, 2014
    Publication date: May 21, 2015
    Inventors: Tomoaki IKEGAMI, Kazuyuki NAKANISHI, Masaki TAMARU
  • Publication number: 20150102420
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Masaki TAMARU, Kazuyuki NAKANISHI, Hidetoshi NISHIMURA
  • Patent number: 8946824
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: February 3, 2015
    Assignee: Panasonic Corporation
    Inventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8946826
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: February 3, 2015
    Assignee: Panasonic Corporation
    Inventors: Masaki Tamaru, Kazuyuki Nakanishi, Hidetoshi Nishimura
  • Publication number: 20150014781
    Abstract: A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring.
    Type: Application
    Filed: September 17, 2014
    Publication date: January 15, 2015
    Inventors: Hiroyuki SHIMBO, Masaki TAMARU
  • Publication number: 20140252653
    Abstract: In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.
    Type: Application
    Filed: May 19, 2014
    Publication date: September 11, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Nana OKAMOTO, Masaki TAMARU, Hidetoshi NISHIMURA
  • Publication number: 20140225164
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Application
    Filed: April 15, 2014
    Publication date: August 14, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Tomoaki IKEGAMI, Kazuyuki NAKANISHI, Masaki TAMARU
  • Patent number: 8791507
    Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: July 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8766322
    Abstract: In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: July 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Nana Okamoto, Masaki Tamaru, Hidetoshi Nishimura
  • Publication number: 20140159160
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Application
    Filed: February 13, 2014
    Publication date: June 12, 2014
    Applicant: Panasonic Corporation
    Inventors: MASAKI TAMARU, KAZUYUKI NAKANISHI, HIDETOSHI NISHIMURA
  • Patent number: 8748987
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: June 10, 2014
    Assignee: Panasonic Corporation
    Inventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8692336
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: April 8, 2014
    Assignee: Panasonic Corporation
    Inventors: Masaki Tamaru, Kazuyuki Nakanishi, Hidetoshi Nishimura
  • Publication number: 20140077307
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Application
    Filed: October 24, 2013
    Publication date: March 20, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Tomoaki IKEGAMI, Kazuyuki NAKANISHI, Masaki TAMARU
  • Patent number: 8669596
    Abstract: In end portions of first and second gate patterns aligned in parallel relation to each other, and opposite end portions of third and fourth gate patterns aligned in parallel relation to each other, the end portion of the first gate pattern extends to be positioned closer to the third and fourth gate patterns than the end portion of the second gate pattern is, and the opposite end portion of the fourth gate pattern extends to be positioned closer to the first and second gate patterns than the opposite end portion of the third gate pattern is.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 11, 2014
    Assignee: Panasonic Corporation
    Inventor: Masaki Tamaru
  • Patent number: 8648392
    Abstract: A plurality of PMOS transistors are provided on a substrate along an X-axis direction such that a gate length direction of each of the PMOS transistors is parallel to the X-axis direction. A plurality of NMOS transistors are provided on the substrate along the X-axis direction such that a gate length direction of each of the NMOS transistors is parallel to the X-axis direction, and each of the plurality of NMOS transistors is opposed to a corresponding one of the PMOS transistors in the Y-axis direction. Gate lines respectively correspond to the PMOS transistors and the NMOS transistors, and are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines passes through gate areas of the PMOS transistors and NMOS transistors which correspond to each of the gate lines.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: February 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Hidetoshi Nishimura, Masaki Tamaru
  • Patent number: 8598668
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: December 3, 2013
    Assignee: Panasonic Corporation
    Inventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
  • Publication number: 20130234211
    Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 12, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Kazuyuki NAKANISHI, Masaki TAMARU
  • Patent number: 8431967
    Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: April 30, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8421125
    Abstract: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: April 16, 2013
    Assignee: Pansonic Corporation
    Inventor: Masaki Tamaru
  • Patent number: 8399928
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: March 19, 2013
    Assignee: Panasonic Corporation
    Inventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru