Patents by Inventor Masaki Tamaru
Masaki Tamaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9362264Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.Type: GrantFiled: December 18, 2014Date of Patent: June 7, 2016Assignee: SOCIONEXT INC.Inventors: Masaki Tamaru, Kazuyuki Nakanishi, Hidetoshi Nishimura
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Patent number: 9343461Abstract: A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring.Type: GrantFiled: September 17, 2014Date of Patent: May 17, 2016Assignee: SOCIONEXT INC.Inventors: Hiroyuki Shimbo, Masaki Tamaru
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Publication number: 20150303216Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.Type: ApplicationFiled: June 29, 2015Publication date: October 22, 2015Inventor: Masaki TAMARU
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Patent number: 9147652Abstract: In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.Type: GrantFiled: May 19, 2014Date of Patent: September 29, 2015Assignee: SOCIONEXT INC.Inventors: Nana Okamoto, Masaki Tamaru, Hidetoshi Nishimura
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Patent number: 9142539Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: GrantFiled: December 17, 2014Date of Patent: September 22, 2015Assignee: SOCIONEXT INC.Inventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
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Patent number: 9099447Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.Type: GrantFiled: October 24, 2012Date of Patent: August 4, 2015Assignee: SOCIONEXT INC.Inventor: Masaki Tamaru
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Publication number: 20150137248Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: ApplicationFiled: December 17, 2014Publication date: May 21, 2015Inventors: Tomoaki IKEGAMI, Kazuyuki NAKANISHI, Masaki TAMARU
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Publication number: 20150102420Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.Type: ApplicationFiled: December 18, 2014Publication date: April 16, 2015Inventors: Masaki TAMARU, Kazuyuki NAKANISHI, Hidetoshi NISHIMURA
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Patent number: 8946826Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.Type: GrantFiled: February 13, 2014Date of Patent: February 3, 2015Assignee: Panasonic CorporationInventors: Masaki Tamaru, Kazuyuki Nakanishi, Hidetoshi Nishimura
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Patent number: 8946824Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: GrantFiled: April 15, 2014Date of Patent: February 3, 2015Assignee: Panasonic CorporationInventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
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Publication number: 20150014781Abstract: A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring.Type: ApplicationFiled: September 17, 2014Publication date: January 15, 2015Inventors: Hiroyuki SHIMBO, Masaki TAMARU
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Publication number: 20140252653Abstract: In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.Type: ApplicationFiled: May 19, 2014Publication date: September 11, 2014Applicant: PANASONIC CORPORATIONInventors: Nana OKAMOTO, Masaki TAMARU, Hidetoshi NISHIMURA
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Publication number: 20140225164Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: ApplicationFiled: April 15, 2014Publication date: August 14, 2014Applicant: PANASONIC CORPORATIONInventors: Tomoaki IKEGAMI, Kazuyuki NAKANISHI, Masaki TAMARU
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Patent number: 8791507Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.Type: GrantFiled: March 18, 2013Date of Patent: July 29, 2014Assignee: Panasonic CorporationInventors: Kazuyuki Nakanishi, Masaki Tamaru
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Patent number: 8766322Abstract: In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.Type: GrantFiled: October 15, 2010Date of Patent: July 1, 2014Assignee: Panasonic CorporationInventors: Nana Okamoto, Masaki Tamaru, Hidetoshi Nishimura
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Publication number: 20140159160Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.Type: ApplicationFiled: February 13, 2014Publication date: June 12, 2014Applicant: Panasonic CorporationInventors: MASAKI TAMARU, KAZUYUKI NAKANISHI, HIDETOSHI NISHIMURA
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Patent number: 8748987Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: GrantFiled: October 24, 2013Date of Patent: June 10, 2014Assignee: Panasonic CorporationInventors: Tomoaki Ikegami, Kazuyuki Nakanishi, Masaki Tamaru
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Patent number: 8692336Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.Type: GrantFiled: March 15, 2012Date of Patent: April 8, 2014Assignee: Panasonic CorporationInventors: Masaki Tamaru, Kazuyuki Nakanishi, Hidetoshi Nishimura
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Publication number: 20140077307Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.Type: ApplicationFiled: October 24, 2013Publication date: March 20, 2014Applicant: PANASONIC CORPORATIONInventors: Tomoaki IKEGAMI, Kazuyuki NAKANISHI, Masaki TAMARU
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Patent number: 8669596Abstract: In end portions of first and second gate patterns aligned in parallel relation to each other, and opposite end portions of third and fourth gate patterns aligned in parallel relation to each other, the end portion of the first gate pattern extends to be positioned closer to the third and fourth gate patterns than the end portion of the second gate pattern is, and the opposite end portion of the fourth gate pattern extends to be positioned closer to the first and second gate patterns than the opposite end portion of the third gate pattern is.Type: GrantFiled: July 27, 2012Date of Patent: March 11, 2014Assignee: Panasonic CorporationInventor: Masaki Tamaru