Patents by Inventor Masaki Tamaru

Masaki Tamaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120306101
    Abstract: A power line structure is implemented which is capable of securing large interconnection resources for signal lines while suppressing a power supply voltage drop. Power supply potential lines and substrate potential lines are formed in a first wiring layer, and power supply strap lines are formed in a wiring layer that is located below the center of the overall height of the wiring layers. Upper via portions are arranged at a lower density in the direction in which the power supply strap lines extend than lower via portions.
    Type: Application
    Filed: August 15, 2012
    Publication date: December 6, 2012
    Applicant: Panasonic Corporation
    Inventor: Masaki TAMARU
  • Publication number: 20120292666
    Abstract: In end portions of first and second gate patterns aligned in parallel relation to each other, and opposite end portions of third and fourth gate patterns aligned in parallel relation to each other, the end portion of the first gate pattern extends to be positioned closer to the third and fourth gate patterns than the end portion of the second gate pattern is, and the opposite end portion of the fourth gate pattern extends to be positioned closer to the first and second gate patterns than the opposite end portion of the third gate pattern is.
    Type: Application
    Filed: July 27, 2012
    Publication date: November 22, 2012
    Applicant: Panasonic Corporation
    Inventor: Masaki TAMARU
  • Publication number: 20120168875
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Application
    Filed: March 15, 2012
    Publication date: July 5, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: MASAKI TAMARU, KAZUYUKI NAKANISHI, HIDETOSHI NISHIMURA
  • Publication number: 20120161241
    Abstract: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern.
    Type: Application
    Filed: March 8, 2012
    Publication date: June 28, 2012
    Applicant: Panasonic Corporation
    Inventor: Masaki TAMARU
  • Patent number: 8198733
    Abstract: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: June 12, 2012
    Assignee: Panasonic Corporation
    Inventor: Masaki Tamaru
  • Patent number: 8143724
    Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: March 27, 2012
    Assignee: Panasonic Corporation
    Inventors: Ritsuko Ozoe, Hiroki Taniguchi, Hidetoshi Nishimura, Masaki Tamaru, Hideaki Kondo
  • Publication number: 20110298138
    Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
    Type: Application
    Filed: August 16, 2011
    Publication date: December 8, 2011
    Applicant: Panasonic Corporation
    Inventors: Ritsuko OZOE, Hiroki Taniguchi, Hidetoshi Nishimura, Masaki Tamaru, Hideaki Kondo
  • Publication number: 20110284964
    Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
    Type: Application
    Filed: July 8, 2011
    Publication date: November 24, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Tomoaki IKEGAMI, Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8022549
    Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: September 20, 2011
    Assignee: Panasonic Corporation
    Inventors: Ritsuko Ozoe, Hiroki Taniguchi, Hidetoshi Nishimura, Masaki Tamaru, Hideaki Kondo
  • Publication number: 20110133253
    Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.
    Type: Application
    Filed: February 3, 2011
    Publication date: June 9, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Kazuyuki NAKANISHI, Masaki Tamaru
  • Publication number: 20110079914
    Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
    Type: Application
    Filed: November 16, 2010
    Publication date: April 7, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Ritsuko OZOE, Hiroki Taniguchi, Hidetoshi Nishimura, Masaki Tamaru, Hideaki Kondo
  • Publication number: 20110073953
    Abstract: A plurality of PMOS transistors are provided on a substrate along an X-axis direction such that a gate length direction of each of the PMOS transistors is parallel to the X-axis direction. A plurality of NMOS transistors are provided on the substrate along the X-axis direction such that a gate length direction of each of the NMOS transistors is parallel to the X-axis direction, and each of the plurality of NMOS transistors is opposed to a corresponding one of the PMOS transistors in the Y-axis direction. Gate lines respectively correspond to the PMOS transistors and the NMOS transistors, and are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines passes through gate areas of the PMOS transistors and NMOS transistors which correspond to each of the gate lines.
    Type: Application
    Filed: November 16, 2010
    Publication date: March 31, 2011
    Applicant: Panasonic Corporation
    Inventors: Hidetoshi NISHIMURA, Masaki TAMARU
  • Publication number: 20110031536
    Abstract: In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.
    Type: Application
    Filed: October 15, 2010
    Publication date: February 10, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Nana Okamoto, Masaki Tamaru, Hidetoshi Nishimura
  • Patent number: 7859023
    Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: December 28, 2010
    Assignee: Panasonic Corporation
    Inventors: Ritsuko Ozoe, Hiroki Taniguchi, Hidetoshi Nishimura, Masaki Tamaru, Hideaki Kondo
  • Patent number: 7737472
    Abstract: A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: June 15, 2010
    Assignee: Panasonic Corporation
    Inventors: Hideaki Kondo, Toshiyuki Moriwaki, Masaki Tamaru, Takashi Andoh
  • Publication number: 20090079087
    Abstract: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern.
    Type: Application
    Filed: November 21, 2008
    Publication date: March 26, 2009
    Applicant: Panasonic Corporation
    Inventor: Masaki Tamaru
  • Patent number: 7465656
    Abstract: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: December 16, 2008
    Assignee: Panasonic Corporation
    Inventor: Masaki Tamaru
  • Publication number: 20080246091
    Abstract: A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows.
    Type: Application
    Filed: April 3, 2008
    Publication date: October 9, 2008
    Inventors: Hideaki Kondo, Toshiyuki Moriwaki, Masaki Tamaru, Takashi Andoh
  • Publication number: 20080246160
    Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 9, 2008
    Inventors: Ritsuko Ozoe, Hiroki Taniguchi, Hidetoshi Nishimura, Masaki Tamaru, Hideaki Kondo
  • Patent number: 7259432
    Abstract: A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the first interlayer insulating film interposed therebetween. The second interlayer insulating film has a lower relative permeability than the first interlayer insulating film.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: August 21, 2007
    Assignee: Matsushita Electric Industrisl Co., Ltd.
    Inventor: Masaki Tamaru