Abstract: A receiver has an oscillator to output an oscillation signal, a receiver to perform reception processing of a reception signal, a phase frequency detector to output a first signal in response to a phase and a frequency of the oscillation signal so as to generate a second signal indicating a reference phase, a differentiator to generate a third signal being a difference between the first signal and the second signal, an oscillator controller to generate a fourth signal for controlling a phase and a frequency of the oscillator, a phase initializer to output an initialization signal for synchronizing a phase of the second signal with a phase of the first signal, a trigger signal generator to output a trigger signal indicating timing with which the phase initializer outputs the initialization signal, and a power supply controller to control whether to supply a power supply voltage.

Abstract: A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.

Abstract: A radio communication device has a local oscillator to generate a local signal, a first mixer to mix a binary continuous phase frequency shift keying signal and the local signal so as to generate a baseband signal, a first filter to remove an unnecessary frequency component included in the baseband signal, a delay device to delay an output signal of the first filter by one symbol, and a wave detector to demodulate the continuous phase frequency shift keying signal, wherein a modulation index m of the continuous phase frequency shift keying signal is a value expressed by m=n+k where 0<n<1 is satisfied and k is an integer of 0 or more, and a frequency of the local signal is a frequency shifted by a frequency corresponding to 0 or 1 of the continuous phase frequency shift keying signal.

Abstract: A pulse detection circuit according to an embodiment includes a conversion circuit, a delay circuit, first and second comparators, a latch, and a generation circuit. The conversion circuit converts an input signal into a thermometer code signal. The delay circuit outputs a delay signal being the thermometer code signal delayed by a predetermined delay time. The first comparator (The second comparator) compares the thermometer code signal with the delay signal and outputs an increase signal (a decrease signal) indicating whether the input signal is larger (smaller) than the input signal before the delay time. Based on the increase signal and the decrease signal, the latch outputs an increase-decrease signal indicating whether the input signal is increasing or decreasing. Based on the thermometer code signal and the increase-decrease signal, the generation circuit generates a pulse detection signal and a pileup detection signal.

Abstract: According to an embodiment, a signal processor includes an integrator, a differentiator, a zero cross detector, a pile-up detector, an event interval detector, a counter, and a creator. The integrator is configured to calculate charge of current from a photoelectric converter for an incident radiation. The differentiator is configured to calculate a differential value of the current. The zero cross detector is configured to detect a zero cross of the differential value. The pile-up detector is configured to detect pile-up of the current based on the zero cross. The event interval detector is configured to detect, based on the zero cross and pile-up, an event interval of the radiation entering. The counter is configured to count, based on the charge and pile-up, the respective numbers of events according to the charge and the event interval. The creator is configured to create histograms for the numbers of events.

Abstract: A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.

Abstract: A receiver has a receiving unit to receive a radio signal, a signal detector to detect a reception signal in each of a plurality of set periods shifted in time to be overlapped in a partial period, and a demodulating unit to perform demodulation processing based on the reception signal. The signal detector has a smoothing unit to smooth the output signal of the receiving unit in each of the plurality of set periods, a comparing unit to output a signal obtained by comparing a level of the smoothed signal, with a threshold value, and an initializing unit to initialize the signal smoothed by the smoothing processing unit, every time the comparing unit compares the smoothed signal with the threshold value, and the demodulating unit performs the demodulation processing based on the smoothed signal determined to be the threshold value or more by the comparing unit.

Abstract: According to an embodiment, an amplifier which amplifies a first signal to output a second signal includes the following elements. The comparator compares the first signal with a third signal to output a fourth signal. The delay circuit delays a fifth signal by a delay time to generate a sixth signal. The first capacitor is connected between a voltage source and a first node that provides the third signal. The second capacitor is connected between the first node and a second node that provides the second signal. The first switch is connected between the second node and a constant current source, and is controlled by the fourth signal and the fifth signal. The second switch is connected between the first node and the second node, and is controlled by the fifth signal and the sixth signal.

Abstract: A radio communication device has an analog control loop unit to generate an analog control signal, a digital control loop unit which has a frequency determined with the frequency of a reference signal and a predetermined frequency setting code signal, a voltage controlled oscillator to generate the voltage control oscillation signal, a data slicer to generate a digital signal obtained by digitally demodulating the reception signal, an automatic offset controller to generate a correction signal, a setting code adjuster to adjust the frequency setting code signal, based on the correction signal, and a direct-current level adjuster to adjust a direct-current level of the digital control signal, based on the correction signal. The data slicer compares the digital control signal adjusted by the direct-current level adjuster, with the threshold value.

Abstract: An oscillator has an oscillator which comprises a first variable capacitor to adjust capacitance based on a first signal and a second variable capacitor to adjust capacitance, generates an oscillation signal having a frequency in accordance with the capacitance of the first variable capacitor and the second variable capacitor, an integer phase detector to detect an integer phase of the oscillation signal, a fractional phase detector to detect a fractional phase of the oscillation signal, a phase error generator to generate a fourth signal indicating a phase error of the oscillation signal, a first filter to extract the first signal in a predetermined frequency band, included in the fourth signal, and to output the first signal, and a second filter to extract the second signal in a predetermined frequency band, included in the fourth signal, and to output the second signal.

Abstract: According to an embodiment, an analog-to-digital converter includes a detection circuit, a first conversion circuit, a second comparator, a delay control circuit, a control circuit. A detection circuit detects a differential time signal corresponding to a delay time by using a comparison signal and a delay comparison signal. A first conversion circuit generates a differential voltage by performing time-to-voltage conversion on the differential time signal. A second comparator generates a digital delay determination signal by comparing the differential voltage and an adjustment target voltage. A delay control circuit generates a delay control signal controlling the delay time in accordance with a delay determination signal. A control circuit generates a control signal by using the delay comparison signal in an analog-to-digital conversion period.

Abstract: According to an embodiment, a circuit includes a shunt and a controller. The shunt shunts input current into a plurality of current paths. The controller controls a gain of current inputted to the shunt by combining the current that is shunted into the current paths by the shunt in combination corresponding to a first signal from the outside or changing a shunt ratio with which the shunt shunts the current into the current paths corresponding to the first signal.

Abstract: A time to digital converter has a counter, a first phase difference detector, a first capacitor, a second capacitor having capacitance N times a capacitance of the first capacitor, a comparator to compare a charge voltage of the first capacitor with a charge voltage of the second capacitor, a first charge controller, a first phase difference arithmetic unit, a second phase difference detector, a second charge controller, a second phase difference arithmetic unit to operate the phase difference between the first signal and the second signal, and a third phase difference arithmetic unit to detect a fractional phase difference between the first signal and the second signal. The first phase difference arithmetic unit operates the phase difference between the first signal and the second signal, based on a reference phase, when the counter suspends a measurement operation.

Abstract: A waveform shaping filter according to one embodiment includes a first resistor, a first transistor, a first capacitor, and a first amplifier. The first resistor includes one end to which a signal current is input and the other end. The first transistor includes a first terminal connected to the other end of the first resistor, a second terminal, and a control terminal. The first capacitor includes one end connected to the other end of the first resistor and the other end. The first amplifier includes an input terminal connected to the one end of the first resistor and an output terminal connected to the control terminal of the first transistor.

Abstract: A successive approximation register analog-to-digital converter includes a capacitance digital-to-analog converter (CDAC) having, a voltage storing circuit connected to an output terminal of the CDAC and including a plurality of capacitors connected in parallel, an output voltage of the CDAC being stored in a selected one of the capacitors, a selector configured to output a voltage stored in the selected one of the capacitors, a comparator configured to compare a voltage input to an input terminal thereof, which is connected to an output terminal of the CDAC, with a reference voltage, and a successive approximation register configured to control the CDAC based on an output of the comparator, and cyclically control the voltage storing circuit and the selector, such that the output of the selector is output to the output terminal one or more cycles after the output voltage was stored in the selected one of the capacitors.

Abstract: An amplifying circuit according to an embodiment includes an input terminal, an output terminal, first and second operational amplifiers, first and second input impedance elements, first to third feedback impedance elements, and an adder. The first (second) operational amplifier includes an inversion input terminal connected to a first (third) node and an output terminal connected to a second (fourth) node. The first (second) input impedance element has one end connected to the input terminal and the other end connected to the first (third) node. The first (second) feedback impedance element has one end connected to the first (third) node and the other end connected to the second (fourth) node. The third feedback impedance element has one end connected to the first node and the other end connected to the fourth node. The adder adds output voltages of the first and second operational amplifiers.

Abstract: A radiation detection apparatus according to an embodiment includes a radiation detector that detects radiation; a first measurer that measures energy of the radiation from the radiation detected by the radiation detector; and a second measurer that measures the number of times that the radiation detector detects the radiation.

Abstract: A readout circuit has a first transistor which have a first terminal, a second terminal, and a control terminal, a second transistor having a first terminal, a second terminal, and a control terminal, a first variable resistance having a first terminal connected to a first reference voltage line, and a second terminal connected to the first terminal of the first transistor, a first resistance having a first terminal connected to the first reference voltage line, and a second terminal connected to the first terminal of the second transistor, a second resistance having a first terminal connected to the second terminal of the first transistor, and a second terminal connected to a second reference voltage line, and a second variable resistance which has a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the second reference voltage line.

Abstract: A phase locked loop has an integer phase detector to detect an integer phase by measuring a cycle number, a fractional phase detector to detect a fractional phase of smaller than one cycle between a reference signal and the oscillation signal, a frequency error generator to generate a frequency error signal between the reference signal and the oscillation signal, a glitch corrector to correct the frequency error signal to generate and output a glitch-corrected signal and the frequency error signal, a phase error generator to generate a phase error by integrating an output signal of the glitch corrector, an oscillator controller to control an oscillation frequency of the oscillation signal, and a synchronous detector to detect whether a phase of the reference signal and a phase of the oscillation signal are in an phase-lock state, and to stop detection of the integer phase when the phase-lock state is detected.

Abstract: A radio communication device has an analog control loop unit to generate an analog control signal that adjusts a phase of a voltage control oscillation signal, a digital control loop unit to generate a digital control signal having a frequency determined by a frequency of a reference signal and a predetermined frequency setting code signal and a phase opposite to a phase of the analog control signal, a voltage controlled oscillator to generate the voltage control oscillation signal, a data slicer to generate a digital signal including the reception signal, an automatic offset controller to generate a correction signal in response to an error between a frequency of the reception signal and a frequency of the voltage control oscillation signal, and a setting code adjuster to adjust the frequency setting code signal, wherein gain of the digital control loop unit is higher than gain of the analog control loop unit.