Abstract: In one embodiment, a differential amplifier circuit includes a first input terminal, a second input terminal, a first transistor, a second transistor, a third transistor, a current source, a first output terminal, a second output terminal, a first passive element, and a second passive element. The first (second) transistor has a control terminal connected to the first (second) input terminal. The third transistor has a control terminal. The control terminal is applied predetermined bias voltage. The current source is connected to a first terminal in each of the first transistor, second transistor, and third transistor. The first (second) output terminal is connected to a second terminal of the first (second) transistor. The first (second) passive element is connected between the first (second) input terminal and the first (second) output terminal.

Abstract: According to an embodiment, a signal processing device includes an integrator, a setting unit, and an analog-to-digital converter. The integrator is configured to integrate an electrical charge corresponding to electromagnetic waves. The integrator includes a capacitor configured to store the electrical charge corresponding to the electromagnetic waves and a discharging circuit configured to discharge the capacitor. The setting unit is configured to set a period of integration of the electrical charge with respect to the integrator. The analog-to-digital converter includes a comparator configured to compare an integration output and a threshold value and a counter configured to output, as digital data of the electrical charge, the number of times for which a value of the integration output becomes not less than the threshold value. The converter is configured to discharge the capacitor during the period of integration by supplying a comparison output of the comparator to the discharging circuit.

Abstract: According to an embodiment, a signal processing device includes an integrator, a first analog-to-digital converter, and a histogram creator. The integrator is configured to integrate an electrical charge corresponding to electromagnetic waves. The first analog-to-digital converter is configured to perform an analog-to-digital conversion operation that generates digital data of the electrical charge using an integration output from the integrator, on a parallel with an integration operation performed by the integrator. The histogram creator is configured to create a histogram that represents an energy distribution of the electromagnetic waves, from the digital data generated by the first analog-to-digital converter.

Abstract: According to an embodiment, a signal processing device includes an integrator, a setting unit, and an analog-to-digital converter. The integrator is configured to integrate an electrical charge corresponding to electromagnetic waves. The integrator includes a capacitor configured to store the electrical charge corresponding to the electromagnetic waves and a discharging circuit configured to discharge the capacitor. The setting unit is configured to set a period of integration of the electrical charge with respect to the integrator. The analog-to-digital converter includes a comparator configured to compare an integration output and a threshold value and a counter configured to output, as digital data of the electrical charge, the number of times for which a value of the integration output becomes not less than the threshold value. The converter is configured to discharge the capacitor during the period of integration by supplying a comparison output of the comparator to the discharging circuit.

Abstract: An A/D converter includes a plurality of AD converting sections that sequentially operate at predetermined intervals. The AD converting section has an ADC that converts an analog signal into a digital signal and outputs the digital signal, a memory that stores, as a specific polarity value, the polarity of a signal obtained by the ADC digitizing an analog signal at a reference voltage, an analog polarity converting circuit that inverts the polarity of the analog signal based on the specific polarity value and a set polarity value, which is previously set, and a digital polarity converting circuit that inverts the polarity of the digital signal based on the specific polarity value and the set polarity value.

Abstract: The first amplifier operates according a first clock, changes voltages of a first terminal and a second terminal from a first fixed voltage to a second fixed voltage according to a voltage of an input signal and a first reference voltage, respectively, when an on period of a first clock starts, and keeps the voltages of the first and second terminals at the second fixed voltage, respectively, after the voltages of the first and second terminals reach the second fixed voltage and until the on period of the first clock ends, and the first comparator generates first and second logic signals that have logical levels different from each other, based on a difference between the voltages of the first and second terminals when the on period of a second clock whose on period at least partially overlaps with that of the first clock starts.

Abstract: An A/D converter includes a plurality of AD converting sections that sequentially operate at predetermined intervals. The AD converting section has an ADC that converts an analog signal into a digital signal and outputs the digital signal, a memory that stores, as a specific polarity value, the polarity of a signal obtained by the ADC digitizing an analog signal at a reference voltage, an analog polarity converting circuit that inverts the polarity of the analog signal based on the specific polarity value and a set polarity value, which is previously set, and a digital polarity converting circuit that inverts the polarity of the digital signal based on the specific polarity value and the set polarity value.

Abstract: This A/D convertor includes: a first D/A conversion unit configured to sample an analog input signal, and to generate a first difference signal by performing successive comparison of the analog input signal based on a reference voltage; a precharge capacitor unit configured to hold the reference voltage; a first comparing unit configured to compare the first difference signal with a reference value to generate a first digital signal; and an amplifying unit configured to calculate by using the first difference signal and the reference voltage to generate a residual signal.

Abstract: According to an embodiment, there are provided a capacitor DAC for generating an output signal in accordance with a connection state of a capacitor element, a reference voltage generation circuit for supplying a reference voltage to the capacitor DAC, a comparator for outputting a comparison result in accordance with the output signal, a successive approximation register for outputting a digital signal in accordance with the comparison result, and a control circuit for controlling a connection state of the capacitor element in accordance with the comparison result and comparing an ideal code with a digital signal obtained by sampling a predetermined voltage, thereby correcting an error of the digital signal.

Abstract: There is provided with a residual signal generating circuit in which the capacitive DA converter generates a first difference signal with respect to an input signal based on a criterion voltage, the criterion voltage being indicative of an input range of the input signal, the reference voltage generating circuit divides the criterion voltage to obtain at least one partial voltage signal, the residual signal generating section generates 2N?1 first residual signal according to a difference between the first difference signal and 2N?1?1 first reference signal, the 2N?1?1 first reference signal being 2N?1?1 partial voltage signal among said at least one partial voltage signal generated by the reference voltage generating circuit, the comparator compares the 2N?1 first residual signal with a fixed voltage to obtain 2N?1 first comparison signal each indicative of a logical value, and the decoder decodes the 2N?1 first comparison signal to obtain first data of N bits.

Abstract: A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.

Abstract: According to some embodiments, there is provided a signal sampling circuit in which the first sampling capacitor is connected to the first sampling switch, the second sampling capacitor is connected to the second sampling switch, the amplifier outputs a positive-side amplified signal by amplifying a signal input to the positive-side input terminal thereof and outputs a negative-side amplified signal by amplifying a signal input to the negative-side input terminal thereof, the first chopper switch is connected to the first sampling capacitor and the positive-side input terminal, the second chopper switch is connected to the first sampling capacitor and the negative-side input terminal, the third chopper switch is connected to the second sampling capacitor and the positive-side input terminal and the fourth chopper switch is connected to the second sampling capacitor and the negative-side input terminal.

Abstract: An automatic gain control circuit configured so that a response time is reduced until a gain converges is disclosed. A variable gain amplifier is configured so that a gain is varied by a first control signal. A detector circuit detects an intensity of an output signal of the variable gain amplifier. A comparator compares an output signal of the detector circuit with a reference signal. An integrator integrates a signal corresponding to an output signal of the comparator, and outputs an integration result to the variable gain amplifier as the first control signal. A loop gain control unit, connected between the comparator and the integrator, is configured so that a loop gain is varied by a second control signal. A level detection unit detects an intensity of an output signal of the integrator and outputs a detection result to the loop gain control unit as the second control signal.

Abstract: There is provided with an A/D conversion apparatus which the first terminal receives a reference voltage signal, the single-ended to differential converter conducts single-ended to differential conversion on the reference voltage signal to obtain a first differential signal, the A/D converter conducts A/D conversion on the first differential signal based on the reference voltage signal to obtain a first digital signal, the digital circuit detects a DC offset which is a difference between the first digital signal and a digital signal, the second terminal receives an input signal, the single-ended to differential converter conducts single-ended to differential conversion on the input signal to acquire a second differential signal, the A/D converter conducts A/D conversion on the second differential signal based on the reference voltage signal to acquire a second digital signal, and the digital circuit subtracts the DC offset from the second digital signal to obtain a third digital signal.

Abstract: According to one embodiment, an analogue to digital converter converts an analogue input signal to a digital output signal. The converter includes an analogue to digital converting unit, a multiplexer, a pseudo-alias signal generator, a gain controller, and an alias signal compensator. The analogue to digital converting unit converts the analogue input signal to a plurality of digital signals. The multiplexer sequentially selects one of the digital signals and outputs the selected digital signal as a multiplexer output. The pseudo-alias signal generator generates a plurality of pseudo-alias signals from the digital signals. The pseudo-alias signal simulates an alias signal component in the multiplexer output. The gain controller generates a plurality of gain control signals by using the pseudo-alias signals. The gain control signal controls gain of the digital output signal. The alias signal compensator compensates the alias signal component by using the gain control signals.

Abstract: According to an embodiment, there are provided a capacitor DAC for generating an output signal in accordance with a connection state of a capacitor element, a reference voltage generation circuit for supplying a reference voltage to the capacitor DAC, a comparator for outputting a comparison result in accordance with the output signal, a successive approximation register for outputting a digital signal in accordance with the comparison result, and a control circuit for controlling a connection state of the capacitor element in accordance with the comparison result and comparing an ideal code with a digital signal obtained by sampling a predetermined voltage, thereby correcting an error of the digital signal.

Abstract: There is provided with a residual signal generating circuit in which the capacitive DA converter generates a first difference signal with respect to an input signal based on a criterion voltage, the criterion voltage being indicative of an input range of the input signal, the reference voltage generating circuit divides the criterion voltage to obtain at least one partial voltage signal, the residual signal generating section generates 2N?1 first residual signal according to a difference between the first difference signal and 2N?1?1 first reference signal, the 2N?1?1 first reference signal being 2N?1?1 partial voltage signal among said at least one partial voltage signal generated by the reference voltage generating circuit, the comparator compares the 2N?1 first residual signal with a fixed voltage to obtain 2N?1 first comparison signal each indicative of a logical value, and the decoder decodes the 2N?1 first comparison signal to obtain first data of N bits.

Abstract: There is provided a successive-approximation A/D converter in which the binary weighted capacitive D/A converter generates a residual signal for each of cycles assigned to each bit of N bits on the basis of an analog input signal and a reference voltage, the first comparator compares a residual signal at a first time point within a cycle with a predetermined voltage to acquire a first comparison result, the register stores the first comparison result therein, the second comparator compares a residual signal at a second time point later than the first time point within the cycle with the predetermined voltage to acquire a second comparison result, the error determining circuit generates an error detection signal when they differ from each other, and the error-correcting circuit inverts and outputs the first comparison result from the register in a case that the error detection signal has been generated.

Abstract: An SAR-ADC includes input and reference terminals, first and second capacitor sets, a dummy capacitor, a comparator, a switch, and a logic. The first and second capacitor sets include first and second capacitors, respectively. The first capacitor has a first capacitance. The second capacitor has a second capacitance. The dummy capacitor has a third capacitance. The comparator compares an output voltage with a ground voltage and outputs a digital output code in accordance with a difference between the output and ground voltages. The switch is connected among the first capacitors of the first and second capacitor sets, and the reference terminal. The logic turns the switch based on the digital output code. The input terminal is located between the first and second capacitors of the first capacitor set. The second capacitor of the first capacitor set is located between the first and second capacitors of the second capacitor set.

Abstract: A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.