Abstract: According to one embodiment, an analogue to digital converter converts an analogue input signal to a digital output signal. The converter includes an analogue to digital converting unit, a multiplexer, a pseudo-alias signal generator, a gain controller, and an alias signal compensator. The analogue to digital converting unit converts the analogue input signal to a plurality of digital signals. The multiplexer sequentially selects one of the digital signals and outputs the selected digital signal as a multiplexer output. The pseudo-alias signal generator generates a plurality of pseudo-alias signals from the digital signals. The pseudo-alias signal simulates an alias signal component in the multiplexer output. The gain controller generates a plurality of gain control signals by using the pseudo-alias signals. The gain control signal controls gain of the digital output signal. The alias signal compensator compensates the alias signal component by using the gain control signals.

Abstract: There is provided with an A/D conversion apparatus which the first terminal receives a reference voltage signal, the single-ended to differential converter conducts single-ended to differential conversion on the reference voltage signal to obtain a first differential signal, the A/D converter conducts A/D conversion on the first differential signal based on the reference voltage signal to obtain a first digital signal, the digital circuit detects a DC offset which is a difference between the first digital signal and a digital signal, the second terminal receives an input signal, the single-ended to differential converter conducts single-ended to differential conversion on the input signal to acquire a second differential signal, the A/D converter conducts A/D conversion on the second differential signal based on the reference voltage signal to acquire a second digital signal, and the digital circuit subtracts the DC offset from the second digital signal to obtain a third digital signal.

Abstract: There is provided a successive-approximation A/D converter in which the binary weighted capacitive D/A converter generates a residual signal for each of cycles assigned to each bit of N bits on the basis of an analog input signal and a reference voltage, the first comparator compares a residual signal at a first time point within a cycle with a predetermined voltage to acquire a first comparison result, the register stores the first comparison result therein, the second comparator compares a residual signal at a second time point later than the first time point within the cycle with the predetermined voltage to acquire a second comparison result, the error determining circuit generates an error detection signal when they differ from each other, and the error-correcting circuit inverts and outputs the first comparison result from the register in a case that the error detection signal has been generated.

Abstract: An analog-to-digital converter includes: weighted capacitors connected to each other at one ends thereof, having a capacitance value weighted at a predetermined ratio, and including a variable capacitance capacitor capable of reducing the capacitance value; a comparator including an input to which the one ends of the weighted capacitors are coupled; switches that connect the other ends different from the one ends to any of an input terminal into which an input signal is input, a reference voltage source used for successive approximation of the input signal, a ground, and an open terminal; a successive approximation controller that controls the switches to sample the input signal onto the weighted capacitors, and use the reference voltage source to generate a comparative voltage for the successive approximation, to thereby execute a successive approximation; and a capacitance controller that controls the switches to reduce a capacitance value of the variable capacitance capacitor.

Abstract: An arithmetic circuit includes: an input terminal for receiving an input signal; plural capacitors; and an amplifier circuit including an amplifying input terminal and an output terminal and configured to amplify a signal input from the amplifying input terminal and output it as an output signal from the output terminal. A first switch circuit becomes conductive based on a first control signal and connects the plural capacitors in parallel between the input terminal and a first voltage terminal for supplying a first voltage. A second switch circuit becomes conductive based on a second control signal and connects a first capacitor of the plural capacitors between the amplifying input terminal and a second voltage terminal for supplying a second voltage to form a first current path and a second capacitor of the plural capacitors between the amplifying input terminal and the output terminal to form a second current path.

Abstract: This A/D convertor includes: a first D/A conversion unit configured to sample an analog input signal, and to generate a first difference signal by performing successive comparison of the analog input signal based on a reference voltage; a precharge capacitor unit configured to hold the reference voltage; a first comparing unit configured to compare the first difference signal with a reference value to generate a first digital signal; and an amplifying unit configured to calculate by using the first difference signal and the reference voltage to generate a residual signal.

Abstract: The SAR control circuit of the successive approximation register A/D converter changes the digital value by the first conversion frequency in a first conversion range according to the comparison result signal, and outputs the digital value. When it is determined that the sample and hold value is out of the first conversion range according to the determination signal, the range setting circuit sets a second conversion range different from the first conversion range.

Abstract: A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected to the reading signal line and which reads the storage information of the memory cell. The reading circuit includes a hold switch connected between the reading signal line and a reading node N and configured to hold the potential of the node N, a capacitor connected between the node N and a ground end, a precharging switch connected between the node N and a power source and configured to charge the capacitor, and an inverter to which the potential of the node N is input to generate a digital signal.

Abstract: An SAR-ADC includes input and reference terminals, first and second capacitor sets, a dummy capacitor, a comparator, a switch, and a logic. The first and second capacitor sets include first and second capacitors, respectively. The first capacitor has a first capacitance. The second capacitor has a second capacitance. The dummy capacitor has a third capacitance. The comparator compares an output voltage with a ground voltage and outputs a digital output code in accordance with a difference between the output and ground voltages. The switch is connected among the first capacitors of the first and second capacitor sets, and the reference terminal. The logic turns the switch based on the digital output code. The input terminal is located between the first and second capacitors of the first capacitor set. The second capacitor of the first capacitor set is located between the first and second capacitors of the second capacitor set.

Abstract: An A/D conversion apparatus includes: a first and a second D/A converter to sample an analog signal and successively compare the analog signal and a reference signal to generate a first and a second comparison signal respectively; a first comparator to compare the first comparison signal generated by the first D/A converter with a benchmark signal; a second comparator to compare the second comparison signal generated by the second D/A converter with the benchmark signal; and a converter to convert the analog signal to a digital signal according to results of the comparisons by the first and second comparators.

Abstract: In a read circuit, a write circuit writes a data to be stored and/or a test data to the memory cell. A control circuit controls the write circuit to write the test data to the memory cell in a first phase, and to write the test data which is same as the first phase to the memory cell in a second phase. An integrator integrates voltages at one terminal of the memory cell during the first phase to obtain a first integrated voltage, and integrates voltages at one terminal of the memory cell during the second phase to obtain a second integrated voltage. A buffer stores the first integrated voltage. A comparator compares the first integrated voltage from the buffer with the second integrated voltage from the integrator to obtain the data.

Abstract: A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected to the reading signal line and which reads the storage information of the memory cell. The reading circuit includes a hold switch connected between the reading signal line and a reading node N and configured to hold the potential of the node N, a capacitor connected between the node N and a ground end, a precharging switch connected between the node N and a power source and configured to charge the capacitor, and an inverter to which the potential of the node N is input to generate a digital signal.

Abstract: A magnetic memory device including a plurality of word lines, a plurality of bit lines which intersect the word lines and are put into groups, a plurality of memory cells which are arranged at intersections between the bit lines and the word lines, each memory cell including a magnetic element and a transistor which are connected in series, a first decoder which sequentially selects the word lines, a second decoder which sequentially drives the bit lines of each group, a weighting adder which performs weighting addition of currents flowing on bit lines in a selected group to generate an added current signal, a current/voltage converter which converts the added current signal into a voltage signal, and an analog-to-digital converter which digitizes the voltage signal.

Abstract: An A/D converting apparatus includes a first A/D converter to sample an analog input signal having a D/A converter to generate a comparative signal for successive comparison with the analog input signal, a signal generator generate a differential signal between the analog input signal and the comparative signal, and a comparator to compare the comparative signal with a standard value to generate a first digital signal exhibiting high-order bit; an amplifier to amplify the differential signal to generate a residue signal; and a second A/D converter to sample the residue signal to generate a second digital signal exhibiting low-order bit.

Abstract: An amplifier circuit includes a current source that is connected between a power supply voltage and an output node and that is turned on when a switching control signal takes a first value and is turned off when the switching control signal takes a second value; a grounded voltage control current source whose amount of current is controlled by an input voltage; a cascode transistor connected between the voltage control current source and the output node; a boost amplifier connected between a gate electrode and a source electrode of the cascode transistor; and a switch that is connected between an output node of the boost amplifier and a bias voltage and that is turned on for a predetermined period of time when a value of the switching control signal is switched from the second value to the first value, to forcefully rise the boost amplifier.

Abstract: An automatic gain control circuit configured so that a response time is reduced until a gain converges is disclosed. A variable gain amplifier is configured so that a gain is varied by a first control signal. A detector circuit detects an intensity of an output signal of the variable gain amplifier. A comparator compares an output signal of the detector circuit with a reference signal. An integrator integrates a signal corresponding to an output signal of the comparator, and outputs an integration result to the variable gain amplifier as the first control signal. A loop gain control unit, connected between the comparator and the integrator, is configured so that a loop gain is varied by a second control signal. A level detection unit detects an intensity of an output signal of the integrator and outputs a detection result to the loop gain control unit as the second control signal.

Abstract: A magnetic memory device includes a plurality of word lines, a plurality of bit lines arranged to intersect with the word lines, an MRAM cell array including a plurality of magnetic random access memory (MRAM) cells arranged at intersection portions between the word lines and the bit lines, a read current source which supplies a read current to the MRAM cells in a read mode, a sense amplifier which detects terminal voltages of the MRAM cells generated by the read current to generate a detection output signal, a latch circuit which latches the detection output signal to output read data, and a data write circuit which supplies a write current to the MRAM cells depending on write data in a write mode to perform writing and which supplies the write current to the MRAM cells depending on the read data in the read mode to perform rewriting.

Abstract: An amplifier circuit includes a current source that is connected between a power supply voltage and an output node and that is turned on when a switching control signal takes a first value and is turned off when the switching control signal takes a second value; a grounded voltage control current source whose amount of current is controlled by an input voltage; a cascode transistor connected between the voltage control current source and the output node; a boost amplifier connected between a gate electrode and a source electrode of the cascode transistor; and a switch that is connected between an output node of the boost amplifier and a bias voltage and that is turned on for a predetermined period of time when a value of the switching control signal is switched from the second value to the first value, to forcefully rise the boost amplifier.

Abstract: A signal processing circuit includes a decimation filter which down-samples over-sampled first three-phase digital signals to obtain second three-phase digital signals, and a converter which subjects the second three-phase digital signals to a three-phase to IQ conversion, and obtains orthogonal digital signals.

Abstract: An A/D conversion apparatus includes: a first and a second D/A converter to sample an analog signal and successively compare the analog signal and a reference signal to generate a first and a second comparison signal respectively; a first comparator to compare the first comparison signal generated by the first D/A converter with a benchmark signal; a second comparator to compare the second comparison signal generated by the second D/A converter with the benchmark signal; and a converter to convert the analog signal to a digital signal according to results of the comparisons by the first and second comparators.