Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.

Abstract: A method of forming a monolithic three-dimensional memory device includes forming a first alternating stack over a substrate, forming an insulating cap layer, forming a first memory opening through the insulating cap layer and the first alternating stack, forming a sacrificial pillar structure in the first memory opening, forming a second alternating stack, forming a second memory opening, forming an inter-stack memory opening, forming a memory film and a first semiconductor channel layer in the inter-stack memory opening, anisotropically etching a horizontal bottom portion of the memory film and the first semiconductor channel layer to expose the substrate at the bottom of the inter-stack memory opening such that damage to portions of the first semiconductor channel layer and the memory film located adjacent to the insulating cap layer is reduced or avoided, and forming a second semiconductor channel layer in contact with the exposed substrate in the inter-stack memory opening.

Abstract: A memory opening is formed through a stack of alternating layers comprising first material layers and second material layers. Sidewall surfaces of the second material layers are laterally recessed with respect to sidewall surfaces of the first material layers within the memory opening. Annular semiconductor material portions can be formed by depositing a semiconductor material from the sidewall surfaces of the second material layers while the semiconductor material does not grow from surfaces of the first material layers. Optionally, an inner portion of each annular semiconductor material portion can be converted into an annular dielectric material portion that includes a dielectric material. A memory film is formed in the memory opening. During removal of the second material layers, the annular semiconductor material portions can be employed as an etch stop material, thereby minimizing collateral etching of the memory film or annular dielectric material portions.

Abstract: Collateral etching of a dielectric material around a trench during formation of a substrate contact via structure can be avoided employing an aluminum oxide layer. The aluminum oxide layer functions as an etch stop layer during an anisotropic etch that removes horizontal portions of an insulating material layer to form an insulating spacer. The aluminum oxide layer may be a conformal or a non-conformal material layer, and may, or may not, include a horizontal portion that overlies an alternating stack of insulating layers and electrically conductive layers. Electrical shorts caused by widening of the top portion of the trench can be avoided through use of the aluminum oxide layer. Memory stack structures can extend through the alternating stack to provide a three-dimensional memory stack structure. A source region can be formed underneath the trench, and the substrate contact via structure can be employed as a source contact via structure.

Abstract: Collateral etching of a dielectric material around a trench during formation of a substrate contact via structure can be avoided employing an aluminum oxide layer. The aluminum oxide layer functions as an etch stop layer during an anisotropic etch that removes horizontal portions of an insulating material layer to form an insulating spacer. The aluminum oxide layer may be a conformal or a non-conformal material layer, and may, or may not, include a horizontal portion that overlies an alternating stack of insulating layers and electrically conductive layers. Electrical shorts caused by widening of the top portion of the trench can be avoided through use of the aluminum oxide layer. Memory stack structures can extend through the alternating stack to provide a three-dimensional memory stack structure. A source region can be formed underneath the trench, and the substrate contact via structure can be employed as a source contact via structure.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures including a memory film and a vertical semiconductor channel and extending through a first region of the alternating stack, and support pillar structures extending through a second region of the alternating stack that is laterally offset from the first region. Each insulating layer includes a respective first insulating material portion having a respective first insulator thickness in the first region of the alternating stack and a respective second insulating material portion having a respective second insulator thickness that is greater than the respective first insulator thickness in the second region.

Abstract: A memory cell can be formed with a pair of charge storage regions. The pair of charge storage regions can be two portions of a charge storage region that are located at the same level and are positioned adjacent to two different control gate electrodes. Alternately, the pair of charge storage regions can be two disjoined structures located on opposite sides of a portion of a semiconductor channel. Yet alternately, the pair of charge storage regions can be two disjoined structures located at the same level, and on two laterally split semiconductor channel. The memory cell can be employed to store two bits of information within the pair of charge storage regions located at the same level within a vertical memory string that employs a single memory opening.

Abstract: Memory openings and support openings are formed through an alternating stack of insulating layers and spacer material layers over a semiconductor substrate. Deposition of a semiconductor material in the support openings during formation of epitaxial channel portions in the memory openings is prevented by Portions of the semiconductor substrate that underlie the support openings are converted into impurity-doped semiconductor material portions. During selective growth of epitaxial channel portions from the semiconductor substrate within the memory openings, growth of a semiconductor material in the support openings is suppressed due to the impurity species in the impurity-doped semiconductor material portions. Memory stack structures and support pillar structures are subsequently formed over the epitaxial channel portions and in the support openings, respectively.

Abstract: A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one embodiment, the material layers can be electrically conductive layers, and a contact via structure can contact the vertically coincident sidewalls. In another embodiment, a sacrificial spacer can be formed on the vertically coincident sidewalls, and the material layers and the sacrificial spacer can be replaced with a conductive material. A contact via structure can be formed on a set of layers electrically shorted by a vertical conductive material portion that is formed in a volume of the spacer. The contact via structure can provide electrical contact to multiple electrically conductive layers.

Abstract: A multilayer electronic component includes a stack and a balun. The stack includes a plurality of stacked dielectric layers and conductor layers. The balun is formed using the stack. The balun includes an unbalanced transmission line and first to fourth balanced transmission lines. The unbalanced transmission line includes a first line portion and a second line portion connected in series. The first and second balanced transmission lines are configured to be electromagnetically coupled to the first line portion. The third and fourth balanced transmission lines are configured to be electromagnetically coupled to the second line portion.

Abstract: A diplexer includes a first bandpass filter provided between an input terminal and a first output terminal and selectively passing a signal in a first frequency band, and a second bandpass filter provided between the input terminal and a second output terminal and selectively passing a signal in a second frequency band. The first bandpass filter includes a plurality of first resonators. The second bandpass filter includes a second resonator and a series resonant circuit. The series resonant circuit is composed of a capacitor provided between the input terminal and the second resonator, and an inductance component of a line that connects the input terminal and the second resonator via the capacitor.

Abstract: A memory opening is formed through a stack of alternating layers comprising first material layers and second material layers. Sidewall surfaces of the second material layers are laterally recessed with respect to sidewall surfaces of the first material layers within the memory opening. Annular semiconductor material portions can be formed by depositing a semiconductor material from the sidewall surfaces of the second material layers while the semiconductor material does not grow from surfaces of the first material layers. Optionally, an inner portion of each annular semiconductor material portion can be converted into an annular dielectric material portion that includes a dielectric material. A memory film is formed in the memory opening. During removal of the second material layers, the annular semiconductor material portions can be employed as an etch stop material, thereby minimizing collateral etching of the memory film or annular dielectric material portions.

Abstract: A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one embodiment, the material layers can be electrically conductive layers, and a contact via structure can contact the vertically coincident sidewalls. In another embodiment, a sacrificial spacer can be formed on the vertically coincident sidewalls, and the material layers and the sacrificial spacer can be replaced with a conductive material. A contact via structure can be formed on a set of layers electrically shorted by a vertical conductive material portion that is formed in a volume of the spacer. The contact via structure can provide electrical contact to multiple electrically conductive layers.

Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.

Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.

Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.

Abstract: A memory cell can be formed with a pair of charge storage regions. The pair of charge storage regions can be two portions of a charge storage region that are located at the same level and are positioned adjacent to two different control gate electrodes. Alternately, the pair of charge storage regions can be two disjoined structures located on opposite sides of a portion of a semiconductor channel. Yet alternately, the pair of charge storage regions can be two disjoined structures located at the same level, and on two laterally split semiconductor channel. The memory cell can be employed to store two bits of information within the pair of charge storage regions located at the same level within a vertical memory string that employs a single memory opening.

Abstract: A diplexer includes a first bandpass filter provided between an input terminal and a first output terminal and selectively passing a signal in a first frequency band, and a second bandpass filter provided between the input terminal and a second output terminal and selectively passing a signal in a second frequency band. The first bandpass filter includes a plurality of first resonators. The second bandpass filter includes a second resonator and a series resonant circuit. The series resonant circuit is composed of a capacitor provided between the input terminal and the second resonator, and an inductance component of a line that connects the input terminal and the second resonator via the capacitor.

Abstract: A method of manufacturing a semiconductor device has forming a first nitride layer over a substrate, forming a first oxide layer on the first nitride layer, forming a second nitride layer on the first oxide layer, forming a photoresist layer over the second nitride layer, forming a opening in the photoresist layer, etching the second nitride layer using the photoresist layer as a mask such that the opening is reached to the first oxide layer, etching the first oxide layer using the second nitride layer as a mask such that the opening is reached to the first nitride layer, etching the first oxide layer such that bottom zone of the opening is increased in diameter, and etching the first nitride layer using the first oxide layer as a mask such that the opening is reached to the substrate thereby to form contact hole reaching to the substrate.

Abstract: In a semiconductor integrated circuit device, from a first power source strap supplying a potential to a first standard cell receiving a supply of the potential, the potential is supplied via a first cell power source line having a constant width. The width of the first cell power source line is determined in accordance with power consumed by the first standard cell and with the number of standard cells that can be placed between the first power source strap and a third power source strap.