THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ANNULAR ETCH-STOP SPACER AND METHOD OF MAKING THEREOF
A method of forming a monolithic three-dimensional memory device includes forming a first alternating stack over a substrate, forming an insulating cap layer, forming a first memory opening through the insulating cap layer and the first alternating stack, forming a sacrificial pillar structure in the first memory opening, forming a second alternating stack, forming a second memory opening, forming an inter-stack memory opening, forming a memory film and a first semiconductor channel layer in the inter-stack memory opening, anisotropically etching a horizontal bottom portion of the memory film and the first semiconductor channel layer to expose the substrate at the bottom of the inter-stack memory opening such that damage to portions of the first semiconductor channel layer and the memory film located adjacent to the insulating cap layer is reduced or avoided, and forming a second semiconductor channel layer in contact with the exposed substrate in the inter-stack memory opening.
The present application is a continuation-in-part application of U.S. application Ser. No. 15/071,575 filed on Mar. 16, 2016, the entire contents of which are incorporated herein by reference.
FIELDThe present disclosure relates generally to the field of three-dimensional memory devices and specifically to three-dimensional memory devices including a vertical stack of multilevel memory arrays and methods of making the same.
BACKGROUNDThree-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
SUMMARYAccording to an aspect of the present disclosure, a monolithic three-dimensional memory device is provided, which comprises: a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate; an insulating cap layer overlying the first alternating stack; a second alternating stack of second insulating layers and second electrically conductive layers overlying the insulating cap layer; a memory stack structure extending through the second alternating stack, the insulating cap layer, and the first alternating stack and comprising a semiconductor channel and a memory film including a plurality of charge storage regions; and an annular spacer located within the insulating cap layer and laterally surrounding the memory stack structure.
According to another aspect of the present disclosure, a method of forming a monolithic three-dimensional memory device includes forming a first alternating stack of first insulating layers and first spacer material layers over a substrate, forming an insulating cap layer over the first alternating stack, forming a first memory opening through the insulating cap layer and the first alternating stack, forming a sacrificial pillar structure in the first memory opening, forming a second alternating stack of second insulating layers and second spacer material layers over the insulating cap layer, forming a second memory opening through the second alternating stack, forming an inter-stack memory opening by removing the sacrificial pillar structure, forming a memory film and a first semiconductor channel layer in the inter-stack memory opening, anisotropically etching a horizontal bottom portion of the memory film and the first semiconductor channel layer to expose the substrate at the bottom of the inter-stack memory opening such that damage to portions of the first semiconductor channel layer and the memory film located adjacent to the insulating cap layer is reduced or avoided, and forming a second semiconductor channel layer in contact with the exposed substrate in the inter-stack memory opening.
According to yet another aspect of the present disclosure, a monolithic three-dimensional memory device is provided, which comprises: a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate; an insulating cap layer overlying the first alternating stack; a second alternating stack of second insulating layers and second electrically conductive layers overlying the insulating cap layer; and a memory stack structure extending through the second alternating stack, the insulating cap layer, and the first alternating stack and comprising a semiconductor channel and a memory film including a plurality of charge storage regions. The insulating cap layer comprises a first concave surface having a first radius of curvature, laterally surrounding the memory stack structure, and adjoined to an upper periphery of a substantially vertical sidewall of the memory stack structure. The insulating cap layer comprises a second concave surface having a second radius of curvature that is greater than the first radius of curvature, laterally surrounding the memory stack structure, and adjoined to an upper periphery of the first concave surface.
According to still another aspect of the present disclosure, a method of forming a device includes forming a first alternating stack of first insulating layers and first spacer material layers over a substrate; forming an insulating cap layer over the first alternating stack; forming a sacrificial material portion in a first memory opening extending through the insulating cap layer and the first alternating stack; performing a set of etch steps at least twice, the set of etch steps comprising a recess etch step that vertically recesses the top surface of the sacrificial material portion downward, and an isotropic etch step that isotropically etches a material of the insulating cap layer selective to the sacrificial material portion, wherein a remaining portion of the sacrificial material portion constitutes a sacrificial pillar structure; forming an fill material portion in an upper portion of the memory opening that overlies the sacrificial pillar structure; forming a second alternating stack of second insulating layers and second spacer material layers over the insulating cap layer; forming a second memory opening through the second alternating stack; and forming an inter-stack memory opening by removing the sacrificial pillar structure from below the second memory opening.
As discussed above, the present disclosure is directed to three-dimensional memory devices including a vertical stack of multilevel memory arrays and methods of making the same, the various aspects of which are described below. An embodiment of the disclosure can be employed to form semiconductor devices such as three-dimensional monolithic memory array devices comprising a plurality of NAND memory strings. The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element.
As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and/or may have one or more layer thereupon, thereabove, and/or therebelow.
A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, with no intervening substrates. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array. In contrast, two-dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device. For example, non-monolithic stacked memories have been constructed by forming memory levels on separate substrates and vertically stacking the memory levels, as described in U.S. Pat. No. 5,915,167 titled “Three Dimensional Structure Memory.” The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays. The various three-dimensional memory devices of the present disclosure include a monolithic three-dimensional NAND string memory device, and can be fabricated employing the various embodiments described herein.
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As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−6 S/cm to 1.0×105 S/cm, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/cm to 1.0×105 S/cm upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105 S/cm. As used herein, an “insulating material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−6 S/cm. All measurements for electrical conductivities are made at the standard condition. Optionally, at least one doped well (not expressly shown) can be formed within the substrate semiconductor layer 10. While the substrate semiconductor layer 10 is alternatively referred to as the substrate 10 in the present disclosure, it is understood that the substrate 10 may optionally include additional material layers (such as a handle substrate and a buried insulator layer as in the case of a semiconductor-on-insulator substrate).
The first exemplary structure includes a device region, in which memory devices can be subsequently formed, and a contact region (not shown), in which stepped surfaces are subsequently formed. As used herein, a “contact region” refers to a region in which contact via structures are to be formed. At least one semiconductor device for a peripheral circuitry can be formed in a peripheral device region (not shown). The at least one semiconductor device can include, for example, one or more field effect transistors. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device.
Optionally, a doped semiconductor well (not separately shown) can be provided in an upper portion of the substrate semiconductor layer 10. The doped semiconductor well can be formed, for example, by implantation of electrical dopants (p-type dopants or n-type dopants) into an upper portion of the substrate semiconductor layer 10, or by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. In one embodiment, the doped semiconductor well can include a single crystalline semiconductor material (e.g., p-well).
An alternating stack of first material layers and second material layers is subsequently formed. Each first material layer can include a first material, and each second material layer can include a second material that is different from the first material. The alternating stack is herein referred to as a first alternating stack. In one embodiment, the first material layers and the second material layers can be first insulating layers 132 and first sacrificial material layers 142, respectively. In one embodiment, each first insulating layer 132 can include a first insulating material, and each first sacrificial material layer 142 can include a first sacrificial material. An alternating plurality of first insulating layers 132 and first sacrificial material layers 142 is formed over the semiconductor substrate layer 10, which is a portion of a substrate. As used herein, a “sacrificial material” refers to a material that is removed during a subsequent processing step.
As used herein, an alternating stack of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of the first elements that is not an end element of the alternating plurality is adjoined by two instances of the second elements on both sides, and each instance of the second elements that is not an end element of the alternating plurality is adjoined by two instances of the first elements on both ends. The first elements may have the same thickness thereamongst, or may have different thicknesses. The second elements may have the same thickness thereamongst, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of the first material layers or with an instance of the second material layers, and may end with an instance of the first material layers or with an instance of the second material layers. In one embodiment, an instance of the first elements and an instance of the second elements may form a unit that is repeated with periodicity within the alternating plurality.
The first alternating stack (132, 142) can include first insulating layers 132 composed of the first material, and first sacrificial material layers 142 composed of the second material, which is different from the first material. The first material of the first insulating layers 132 can be at least one insulating material. Insulating materials that can be employed for the first insulating layers 132 include, but are not limited to silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first insulating layers 132 can be silicon oxide.
The second material of the first sacrificial material layers 142 is a sacrificial material that can be removed selective to the first material of the first insulating layers 132. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material.
The first sacrificial material layers 142 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layers 142 can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device. In one embodiment, the first sacrificial material layers 142 can be material layers that comprise silicon nitride.
In one embodiment, the first insulating layers 132 can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial material layers. The first material of the first insulating layers 132 can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the first insulating layers 132, tetraethylorthosilicate (TEOS) can be employed as the precursor material for the CVD process. The second material of the first sacrificial material layers 142 can be formed, for example, CVD or atomic layer deposition (ALD).
The thicknesses of the first insulating layers 132 and the first sacrificial material layers 142 can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each first insulating layer 132 and for each first sacrificial material layer 142. The number of repetitions of the pairs of a first insulating layer 132 and a first sacrificial material layer 142 can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. In one embodiment, each first sacrificial material layer 142 in the first alternating stack (132, 142) can have a uniform thickness that is substantially invariant within each respective first sacrificial material layer 142.
A first insulating cap layer 170A is sequentially formed. The first insulating cap layer 170A includes a dielectric material, which can be any dielectric material that can be employed for the first insulating layers 132. In one embodiment, the first insulating cap layer 170A includes the same dielectric material as the first insulating layers 132. The thickness of the insulating cap layer 170A can be in a range from 20 nm to 300 nm, although lesser and greater thicknesses can also be employed.
Optionally, the first insulating cap layer 170A and the first alternating stack (132, 142) can be patterned to form first stepped surfaces in a contact region (not shown). The contact region includes a first stepped area in which the first stepped surfaces are formed, and a second stepped area in which additional stepped surfaces are to be subsequently formed in a second tier structure (to be subsequently formed over a first tier structure). The first stepped surfaces can be formed, for example, by forming a mask layer with an opening therein, etching a cavity within the levels of the first insulating cap layer 170A, and iteratively expanding the etched area and vertically recessing the cavity by etching each pair of a first insulating layer 132 and a first sacrificial material layer 142 located directly underneath the bottom surface of the etched cavity within the etched area. A dielectric material can be deposited to fill the first stepped cavity to form a first retro-stepped dielectric material portion (not shown). As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present.
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In one embodiment, the chemistry of the anisotropic etch process employed to etch through the materials of the first alternating stack (132, 142) can alternate to optimize etching of the first and second materials in the first alternating stack (132, 142). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the lower memory openings 121 can be substantially vertical, or can be tapered. Subsequently, the patterned lithographic material stack can be subsequently removed, for example, by ashing.
A selective epitaxy process can be performed to deposit a semiconductor material on physically exposed semiconductor surfaces. Specifically, epitaxial channel portions 11 can grow from the semiconductor surfaces at the bottom of the lower memory openings 121 during the selective epitaxy process. The epitaxial channel portions 11 comprise a single crystalline semiconductor material in epitaxial alignment with the single crystalline substrate semiconductor material of the substrate semiconductor layer 10.
In one embodiment, the deposited semiconductor material may be doped with in-situ doping of a p-type dopant or an n-type dopant. Thus, the epitaxial channel portions 11 can be doped with electrical dopants of a suitable conductivity type. In one embodiment, the substrate semiconductor layer 10 and the epitaxial channel portions 11 can have a doping of the first conductivity type (e.g., p-type). The epitaxial channel portions 11 may comprise silicon.
The selective epitaxy process can be performed, for example, by sequentially or simultaneously flowing a reactant gas (such as SiH4, SiH2Cl2, SiHCl3, SiCl4, Si2H6, GeH4, Ge2H6, other semiconductor precursor gases, or combinations there) with an etchant gas (such as HCl). The deposition rate of the semiconductor material on amorphous surfaces (such as the surfaces of dielectric materials) is less than the etch rate of the semiconductor material by the etchant, while the deposition rate of the semiconductor material on crystalline surfaces (such as the top surface of the substrate semiconductor layer 10) is greater than the etch rate of the semiconductor material by the etchant. Thus, the semiconductor material is deposited only on the semiconductor surface, which is the physically exposed portion of the top surface of the substrate semiconductor layer 10. The process conditions (such as the deposition temperature, the partial pressure of the various gases in a process chamber, etc.) can be selected such that the deposited semiconductor material is epitaxial, i.e., single crystalline silicon or another semiconductor material with atomic alignment with the single crystalline structure of the substrate semiconductor layer 10 (e.g., p-well). Each epitaxial channel portion 11 can be formed at a bottom portion of a respective lower memory opening 121.
Subsequently, a thermal oxidation process or a plasma oxidation process can be performed to oxidize a surface portion of each epitaxial channel portion 11, thereby converting the surface portion into a respective semiconductor oxide portion 13. The thickness of the semiconductor oxide portion 13 can be in a range from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed.
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In one embodiment, the sacrificial fill material layer 131L can include an undoped semiconductor material. As used herein, an “undoped” semiconductor material refers to a semiconductor material that is intrinsic, or not intentionally doped, and thus, having a low dopant concentration such as less than 1.0×1017/cm3. In one embodiment, the sacrificial fill material layer 131L can be an amorphous or polycrystalline silicon layer including undoped amorphous or polycrystalline silicon.
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The spacer material layer can be anisotropically etched using any suitable sidewall spacer anisotropic etch to remove horizontal portions of the spacer material layer from above the top surfaces of the sacrificial pillar structures 3A and from portions of the recessed top surface of the first insulating cap layer 170A that are spaced from the sidewalls of the sacrificial pillar structures 3A by more than the thickness of the spacer material layer. Each remaining annular portion of the spacer material layer constitutes an annular spacer 172. The lateral thickness of each annular spacer 172, as measured at the bottom portion thereof between the outer sidewall and a most proximate portion of the inner sidewall, can be substantially the same as the initial thickness of the sacrificial material layer.
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Subsequently, the second insulating cap layer 170B can be planarized to remove portions above a horizontal plane including the top surfaces of the sacrificial pillar structures 3A. The planarization of the second insulating cap layer 170B can be performed, for example, by chemical mechanical planarization employing the sacrificial pillar structures 3A as stopping structures. In one embodiment, a planarized top surface of the second insulating cap layer 170B can be within a same horizontal plane as the topmost surfaces of each annular spacer 172. The first insulating cap layer 172A and the second insulating cap layer 172B are collectively referred to a first insulating cap layer 170. The first alternating stack (132, 142), the first insulating cap layer 170, and elements embedded in the first alternating stack (132, 142) (e.g., elements 3A and 172) collectively constitute a first tier structure (132, 142, 170, 3A).
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In one embodiment, the third material layers can be second insulating layers 232 and the fourth material layers can be second spacer material layers that provide vertical spacing between each vertically neighboring pair of the second insulating layers 232. In one embodiment, the third material layers and the fourth material layers can be second insulating layers 232 and second sacrificial material layers 242, respectively. The third material of the second insulating layers 232 may be at least one insulating material. The fourth material of the second sacrificial material layers 242 may be a sacrificial material that can be removed selective to the third material of the second insulating layers 232. The second sacrificial material layers 242 may comprise an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layers 242 can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device.
In one embodiment, each second insulating layer 232 can include a second insulating material, and each second sacrificial material layer 242 can include a second sacrificial material. In this case, the second stack (232, 242) can include an alternating plurality of second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layers 232 can be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layers 242 can be formed, for example, CVD or atomic layer deposition (ALD).
The third material of the second insulating layers 232 can be at least one insulating material. Insulating materials that can be employed for the second insulating layers 232 can be any material that can be employed for the first insulating layers 132. The fourth material of the second sacrificial material layers 242 is a sacrificial material that can be removed selective to the third material of the second insulating layers 232. Sacrificial materials that can be employed for the second sacrificial material layers 242 can be any material that can be employed for the first sacrificial material layers 142. In one embodiment, the second insulating material can be the same as the first insulating material, and the second sacrificial material can be the same as the first sacrificial material.
The thicknesses of the second insulating layers 232 and the second sacrificial material layers 242 can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each second insulating layer 232 and for each second sacrificial material layer 242. The number of repetitions of the pairs of a second insulating layer 232 and a second sacrificial material layer 242 can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. In one embodiment, each second sacrificial material layer 242 in the second stack (232, 242) can have a uniform thickness that is substantially invariant within each respective second sacrificial material layer 242.
A second insulating cap layer 270 can be subsequently formed over the second stack (232, 242). The second insulating cap layer 270 includes a dielectric material that is different from the material of the second sacrificial material layers 242. In one embodiment, the insulating cap layer 70 can include silicon oxide. In one embodiment, the first and second sacrificial material layers (142, 242) can comprise silicon nitride. Optionally, second stepped surfaces (not shown) can be region in the contact region in the same manner as formation of the first stepped surfaces. A second retro-stepped dielectric material portion may be formed over the second stepped surfaces.
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In one embodiment, the chemistry of the anisotropic etch process employed to etch through the materials of the second stack (232, 242) can alternate to optimize etching of the third and fourth materials in the second stack (232, 242). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the second memory openings 221 can be substantially vertical, or can be tapered. In one embodiment, the sacrificial pillar structures 3A may be employed as stopping structures for the anisotropic etch process that forms the second memory openings 221. An overetch into upper portions of the sacrificial pillar structures 3A can occur during the anisotropic etch. In other words, the second memory openings 221 can be formed employing an anisotropic etch process that stops at a height between a first horizontal plane including topmost surfaces of the annular spacers 172 and a second horizontal plane including bottom surfaces of the annular spacers 172.
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In one embodiment, removal of the sacrificial pillar structures 3A can be performed selective to the annular spacers 172 such that the spacers 172 are substantially retained employing an etch chemistry that provides differential etch rates that depend on the concentration of electrical dopants (e.g., which etches the pillar structures 3A at a rate that is at least 50 times greater, such as 100 to 150 times greater, than the spacers 172). In one embodiment, the sacrificial pillar structures 3A can include a first semiconductor material that does not include electrical dopants or includes electrical dopants at an atomic concentration less than 1.0×1017/cm3, and the annular spacers 172 can include a second semiconductor material that includes electrical dopants at an atomic concentration greater than 1.0×1018/cm3. In one embodiment, the sacrificial pillar structures 3A can include amorphous or polycrystalline silicon that does not include electrical dopants or includes electrical dopants at an atomic concentration less than 1.0×1017/cm3, the annular spacers 172 can include amorphous or polycrystalline silicon that includes electrical dopants at an atomic concentration greater than 1.0×1018/cm3, and removal of the sacrificial pillar structures 3A selective to the annular spacers 172 can be performed employing hot trimethyl-2 hydroxyethyl ammonium hydroxide.
Subsequently, semiconductor oxide portions 13 may be optionally removed to physically expose the top surfaces of the epitaxial channel portions 11. In one embodiment, the semiconductor oxide portions 13 can be removed by a wet etch employing hydrofluoric acid. In another embodiment, the semiconductor oxide portions are not removed.
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The blocking dielectric layer 52 includes a blocking dielectric layer material such as silicon oxide, a dielectric metal oxide (such as aluminum oxide), or a combination thereof. Alternatively, the blocking dielectric layer 52 may be omitted during this processing step and instead be formed through backside recesses as will be described in more detail below. In one embodiment, the memory material layer 54 can be a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride.
The memory material layer 54 can be formed as a single memory material layer of homogeneous composition, or can include a stack of multiple memory material layers. The multiple memory material layers, if employed, can comprise a plurality of spaced-apart floating gate material layers that contain conductive materials (e.g., metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof) and/or semiconductor materials (e.g., polycrystalline or amorphous semiconductor material including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or additionally, the memory material layer 54 may comprise an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the memory material layer 54 may comprise conductive nanoparticles such as metal nanoparticles, which can be, for example, ruthenium nanoparticles. The memory material layer 54 can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. The thickness of the memory material layer 54 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. Each portion of the memory material layer 54 located at the levels of the electrically conductive layers (146, 246).
The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. The thickness of the tunneling dielectric layer 56 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.
A first semiconductor channel layer can be deposited over the memory films 50 by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The first semiconductor channel layer and the memory films 50 can be anisotropically etched to remove horizontal portions thereof. A horizontal bottom portion of each memory film 50 can be removed from the bottom of each memory opening. Each remaining portion of the first semiconductor channel layer constitutes a first semiconductor channel 601. The first semiconductor channels can include a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channels 601 can include amorphous silicon or polysilicon. The memory film 50 and the first semiconductor channel 601 are anisotropically etched to remove the memory film 50 and the first semiconductor channel 601 (and layer 13 if present) at the bottom of the memory opening 49 to expose the structures 11, while leaving the memory film 50 and the first semiconductor channel 601 on the sidewalls of the memory opening 49.
A second semiconductor channel layer can be deposited on the first semiconductor channels 601 (i.e., the remaining vertical portions of the first semiconductor channel layer) and on top surface of the epitaxial channel portions 11 (or of the substrate semiconductor layer 10 in case the epitaxial channel portions 11 are not present). The second semiconductor channel layer includes a semiconductor material, which can be any semiconductor material that can be employed for the first semiconductor channel layer. The first and second semiconductor channel layers can have a doping of the first conductivity type (i.e., the same conductivity type as the substrate semiconductor layer 10) or can be substantially intrinsic, i.e., having a dopant concentration that does not exceed 1.0×1017/cm3. In one embodiment, the second semiconductor channel layer can include amorphous silicon or polysilicon. The thickness of the second semiconductor channel layer can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed.
A dielectric material can be deposited in cavities surrounded by the second semiconductor channel layer, and subsequently recessed below the top surface of the second dielectric tier cap layer 270. Each remaining portion of the dielectric material in the memory openings constitutes a dielectric core 62. A doped semiconductor material having a second conductivity type (which is the opposite of the first conductivity type) can be deposited over the dielectric cores 62 and within the cavities in the memory openings to form drain regions 63. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material can be removed from above the top surface of the second insulating cap layer 270, for example, by chemical mechanical planarization (CMP) or a recess etch to form the drain region 63. Each remaining portion of the second semiconductor channel layer constitutes a second semiconductor channel 602. A combination of a first semiconductor channel 601 and a second semiconductor channel 602 inside a memory opening constitutes a vertical semiconductor channel 60.
Each memory film 50 can include a blocking dielectric layer 52 contacting a sidewall of the memory opening, a plurality of charge storage regions (embodied as portions of a memory material layer 54 at each level of the sacrificial material layers (142, 242)) located on an inner sidewall of the blocking dielectric layer 52, and a tunneling dielectric layer 56 located inside the plurality of charge storage regions.
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At least one backside trench 79 can be formed through the upper and first tier structures, for example, by applying a photoresist layer (not shown), lithographically patterning the photoresist layer, and transferring the pattern in the photoresist layer through the upper and first tier structures employing an anisotropic etch. The anisotropic etch that forms the at least one backside trench 79 can stop on the substrate 10. The photoresist layer can be subsequently removed, for example, by ashing.
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The isotropic etch process can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trench 79. For example, if the first and second sacrificial material layers (142, 242) include silicon nitride, the etch process can be a wet etch process in which the first exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art.
Each of the first and second backside recesses (143, 243) can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the first and second backside recesses (143, 243) can be greater than the height of the respective backside recess (143, 243). A plurality of first backside recesses 143 can be formed in the volumes from which the material of the first sacrificial material layers 142 is removed. A plurality of second backside recesses 243 can be formed in the volumes from which the material of the second sacrificial material layers 242 is removed. Each of the first and second backside recesses (143, 243) can extend substantially parallel to the top surface of the substrate 10. A backside recess (143, 243) can be vertically bounded by a top surface of an underlying insulating layer (132 or 232) and a bottom surface of an overlying insulating layer (132 or 232). In one embodiment, each of the first and second backside recesses (143, 243) can have a uniform height throughout.
In one embodiment, a sidewall surface of each epitaxial channel portion 11 and a top surface of a semiconductor material layer in the substrate (i.e., the substrate semiconductor layer 10) can be physically exposed below the bottommost first backside recess 143 after removal of the first and second sacrificial material layers (142, 242).
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Referring to
At least one conductive material can be deposited in the plurality of backside recesses (143, 243), on the sidewalls of the backside trench 79, and over the planarization dielectric layer 280. The at least one conductive material can include at least one metallic material, i.e., an electrically conductive material that includes at least one metallic element.
A plurality of first electrically conductive layers 146 can be formed in the plurality of first backside recesses 143, a plurality of second electrically conductive layers 246 can be formed in the plurality of second backside recesses 243, and a continuous metallic material layer 46L can be formed on the sidewalls of each backside trench 79 and over the planarization dielectric layer 280. In embodiments in which the first spacer material layers and the second spacer material layers are provided as first sacrificial material layers 142 and second sacrificial material layers 242, the first and second sacrificial material layers (142, 242) can be replaced with the first and second conductive material layers (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced with a portion of the backside blocking dielectric layer and a first electrically conductive layer 146, and each second sacrificial material layer 242 can be replaced with a portion of the backside blocking dielectric layer and a second electrically conductive layer 246. A backside cavity is present in the portion of each backside trench 79 that is not filled with the continuous metallic material layer 46L.
The metallic material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The metallic material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof. Non-limiting exemplary metallic materials that can be deposited in the backside recesses (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. In one embodiment, the metallic material can comprise a metal such as tungsten and/or metal nitride. In one embodiment, the metallic material for filling the backside recesses (143, 243) can be a combination of titanium nitride layer and a tungsten fill material. In one embodiment, the metallic material can be deposited by chemical vapor deposition or atomic layer deposition.
Referring to
Each electrically conductive layer (146, 246) except the bottommost electrically conductive layer (i.e., the bottommost first electrically conductive layer 146) can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The control gate electrodes within each electrically conductive layer (146, 246) are the control gate electrodes for a vertical memory device including the memory stack structure 55.
The bottommost first electrically conductive layer 146 can be a source select gate electrode located over the gate dielectric layer 12, which can control activation of a horizontal channel portion of a semiconductor channel that extends between a source region 61 (which is previously formed or which will be subsequently formed underneath each backside trench 79) and drain regions 63. In one embodiment, the backside blocking dielectric layer may be present as a single continuous material layer. In another embodiment, the vertical portions of the backside blocking dielectric layer may be removed from within the backside trenches 79, and the backside blocking dielectric layer can have a plurality of physically disjoined backside blocking dielectric layer portions that are located at each level of the electrically conductive layers (146, 246).
Dopants of a second conductivity type, which is the opposite of the first conductivity type of the substrate semiconductor layer 10, can be implanted into a surface portion of the substrate semiconductor layer 10 to form a source region 61 underneath the bottom surface of each backside trench 79. An insulating spacer 74 including a dielectric material can be formed at the periphery of each backside trench 79, for example, by deposition of a conformal insulating material (such as silicon oxide) and a subsequent anisotropic etch. The planarization dielectric layer 280 may be thinned due to a collateral etch during the anisotropic etch that removes the vertical portions of horizontal portions of the deposited conformal insulating material.
A backside contact via structure 76 can be formed in the remaining volume of each backside trench 79, for example, by deposition of at least one conductive material and removal of excess portions of the deposited at least one conductive material from above a horizontal plane including the top surface of the planarization dielectric layer 80 by a planarization process such as chemical mechanical planarization or a recess etch. Optionally, each backside contact via structure 76 may include multiple backside contact via portions such as a lower backside contact via portion and an upper backside contact via portion. In an illustrative example, the lower backside contact via portion can include a doped semiconductor material (such as doped polysilicon), and can be formed by depositing the doped semiconductor material layer to fill the backside trenches 79 and removing the deposited doped semiconductor material from upper portions of the backside trenches 79. The upper backside contact via portion can include at least one metallic material (such as a combination of a TiN liner and a W fill material), and can be formed by depositing the at least one metallic material above the lower backside contact via portions, and removing an excess portion of the at least one metallic material from above the horizontal plane including the top surface of the planarization dielectric layer 280. The planarization dielectric layer 280 can be thinned and removed during a latter part of the planarization process, which may employ chemical mechanical planarization (CMP), a recess etch, or a combination thereof. Each backside contact via structure 76 can be formed through the at least one tier structure (132, 146, 232, 246) and on a source region 61, which may be a source region. The top surface of each backside contact via structure 76 can be formed within the horizontal plane that includes the top surfaces of the memory stack structures 55.
Referring to
The processing steps of
Referring to
In one embodiment, removal of the pillar structure stacks (3A, 3B) can be performed selective to the annular spacers 172 employing an etch chemistry that provides differential etch rates that depend on the concentration of electrical dopants. In one embodiment, the pillar structure stacks (3A, 3B) can include a first semiconductor material that does not include electrical dopants or includes electrical dopants at an atomic concentration less than 1.0×1017/cm3, and the annular spacers 172 can include a second semiconductor material that includes electrical dopants at an atomic concentration greater than 1.0×1018/cm3. In one embodiment, the pillar structure stacks (3A, 3B) can include amorphous or polycrystalline silicon that does not include electrical dopants or includes electrical dopants at an atomic concentration less than 1.0×1017/cm3, the annular spacers 172 can include amorphous or polycrystalline silicon that includes electrical dopants at an atomic concentration greater than 1.0×1018/cm3, and removal of the pillar structure stacks (3A, 3B) selective to the annular spacers 172 can be performed employing hot trimethyl-2 hydroxyethyl ammonium hydroxide.
Referring to
In one embodiment, an inner sidewall of the annular spacer 172 contacts a portion of an outer sidewall of the memory film 50. In one embodiment, a bottom surface of the annular spacer 172 is vertically spaced from a bottom surface of the insulating cap layer 170. In one embodiment, the annular spacer 172 has a horizontal bottom surface and a tapered sidewall surface. In one embodiment, the insulating cap layer 170 can comprise a first insulating cap layer 170A having a top surface that is coplanar with a bottom surface of the annular spacer 172, and a second insulating cap layer 170B having a top surface that is coplanar with a topmost surface of the annular spacer 172. In one embodiment, the annular spacer 172 can comprise a doped semiconductor material.
In one embodiment, the memory opening 49 can have a first horizontal ledge 49A at an interface between the insulating cap layer 170 and the second alternating stack (232, 246), and a second horizontal ledge 49B that contacts a horizontal surface of the annular spacer 172 between a top surface of the annular spacer 172 and a bottom surface of the annular spacer 172, as illustrated in
According to another aspect of the present disclosure, a second exemplary structure according to an embodiment of the present disclosure can be derived from the first exemplary structure of
Exemplary implementation of the set of etch steps twice is illustrated in
Referring to
Referring to
Referring to
Optionally, the processing steps of
At least two concave sidewalls are formed around each recess region 169, which is a portion of the volume of the expanded first memory opening 121. In one embodiment, the at least two concave sidewalls can include a first concave sidewall having a first radius of curvature R1 and adjoining a substantially vertical sidewall of the first insulating cap layer 170A that contacts a vertical sidewall of a respective sacrificial pillar structure 3A. The at least two concave sidewalls can further include a second concave sidewall having a second radius of curvature R2 that is greater than the first radius of curvature R1 and adjoining an upper edge (i.e., the top periphery) of the first concave sidewall.
Referring to
In one embodiment, the fill material portions 3B includes a material that can function as an etch stop material during a subsequent anisotropic etch process to be employed to form second memory openings through a second tier structure during a subsequent processing step. In this case, the fill material portions 3B can be etch stop material portions. In an illustrative example, the fill material portions 3B can include a doped semiconductor material (such as doped polysilicon or doped amorphous silicon) or an undoped semiconductor material (such as undoped polysilicon or undoped amorphous silicon). The sacrificial pillar structures 3A can include a material that can be removed concurrently with removal of the fill material portions 3B, or a material that can be removed selective to the fill material portions 3B. For example, if the sacrificial pillar structures 3A include a silicon-germanium alloy, the fill material portions 3B can include silicon to enable selective removal of the sacrificial pillar structures 3A. If the sacrificial pillar structures 3A include undoped silicon, the fill material portions 3B can include boron-doped silicon to enable selective removal of the sacrificial pillar structures. In some embodiments, the fill material portions 3B and the sacrificial pillar structures 3A include materials that can be simultaneously etched.
Referring to
Referring to
The fill material portions 3B are subsequently removed, wholly or in part, to physically expose top surfaces of the sacrificial pillar structures 3A. The sacrificial pillar structures 3A are subsequently removed selective to the materials of the first alternating stack (132, 142), the second alternating stack (232, 242), and the first and second insulating cap layers (170A, 270). Any remaining portion of the fill material portions 3B can be removed, for example, employing an etch including an isotropic component prior to, during, or after, removal of the sacrificial pillar structures 3A. An inter-stack memory opening 49 is formed by removing the underlying sacrificial pillar structure 3A from below each second memory opening. Subsequently, the semiconductor oxide portions 13 can be removed, for example, by an etch process that employs HF chemistry. A top surface of an epitaxial channel portion 11 can be physically exposed at the bottom of each inter-stack memory opening 49.
Referring to
The second exemplary structure includes a monolithic three-dimensional memory device that includes a first alternating stack of first insulating layers 132 and first electrically conductive layers 146 located over a top surface of a substrate 10; an insulating cap layer 170A overlying the first alternating stack (132, 146); a second alternating stack of second insulating layers 232 and second electrically conductive layers 246 overlying the insulating cap layer 170A; and a memory stack structure 55 extending through the second alternating stack (232, 246), the insulating cap layer 170A, and the first alternating stack (132, 146) and comprising a semiconductor channel 60 and a memory film 50 including a plurality of charge storage regions (as embodied as portions of the memory material layer 54 located at levels of the electrically conductive layers (146, 246)). The insulating cap layer 170A comprises a first concave surface having a first radius of curvature R1, laterally surrounding the memory stack structure 55, and adjoined to an upper periphery of a substantially vertical sidewall of the memory stack structure 55 (that contacts the insulating cap layer 170A). The insulating cap layer 170A also comprises a second concave surface having a second radius of curvature R2 that is greater than the first radius of curvature R1, laterally surrounding the memory stack structure 55, and adjoined to an upper periphery of the first concave surface.
In one embodiment, an upper periphery of the second concave surface is adjoined to a lower periphery of a substantially vertical sidewall of the insulating cap layer 170A, of which the upper periphery is adjoined to the top surface of the insulating cap layer 170A. A first convex sidewall of the memory stack structure 55 contacts the first concave sidewall of the insulating cap layer 170A, and a second convex sidewall of the memory stack structure 55 contacts the second concave sidewall of the insulating cap layer 170A. Each the memory stack structure 55 can have a first periphery PR1 at which a substantially vertical outer sidewall of the structure 55 adjoins a top surface of the structure 55, and each memory stack structure 55 can have a second periphery PR2 at which a substantially vertical inner sidewall of the structure 55 adjoins a convex bottom surface of the structure 55.
The convex sidewall(s) of the structure 55 forms a thicker, sloped (i.e., tapered) surface which extends between a vertical and horizontal direction in structure 55 at the junction of openings 121 and 221 in layer 170A. This thicker, sloped surface of structure 55 prevents or reduces etching damage during the anisotropic etch of the horizontal surface of the bottom of the structure 55 at the interface of opening 121 and structure 11. In other words, the damage to the sloped surface of the structure 55 is reduced or avoided during the anisotropic etch of the first semiconductor channel layer 601 and the memory films 50 to remove the horizontal bottom portion of each memory film 50 from the bottom of each memory opening before the step of forming the second semiconductor channel layer 602 in contact with the structure 11. As shown in
Referring to
A memory stack structure 55 can be formed on each annular spacer 472. Upon formation of the memory stack structures 55, the dielectric cores 62, and the drain regions 63, each annular spacer 472 laterally surrounds a respective memory stack structure 55. A first convex sidewall of the annular spacer 472 can contact the first concave sidewall of the insulating cap layer 170A, and a second convex sidewall of the annular spacer 472 can contact the second concave sidewall of the insulating cap layer 170A.
The alternate embodiment of the second exemplary structure includes a monolithic three-dimensional memory device, which comprises: a first alternating stack of first insulating layers 132 and first electrically conductive layers 146 located over a top surface of a substrate 10; an insulating cap layer 170A overlying the first alternating stack (132, 146); a second alternating stack of second insulating layers 232 and second electrically conductive layers 246 overlying the insulating cap layer 170A; a memory stack structure 55 extending through the second alternating stack (232, 246), the insulating cap layer 170A, and the first alternating stack (132, 146) and comprising a semiconductor channel 60 and a memory film 50 including a plurality of charge storage regions; and an annular spacer 472 located within the insulating cap layer 170A and laterally surrounding the memory stack structure 55. In one embodiment, the annular spacer 472 can have a planar top surface that contacts a bottommost layer within the second alternating stack (232, 246). In one embodiment, the annular spacer 472 can have a bottommost surface that is located above a horizontal plane including an interface between the first alternating stack (132, 146) and the insulating cap layer 170A. In one embodiment, a substantially vertical outer sidewall of the annular spacer 472 can laterally protrude farther outward than any portion of the memory stack structure 55 within the first alternating stack (132, 146). In one embodiment, the annular spacer 472 can include a material selected from a doped semiconductor material (such as undoped silicon or doped silicon) and a dielectric material (such as silicon oxide, silicon nitride, or a dielectric metal oxide).
In one embodiment, each annular spacer 472 can have a first periphery PR1 at which a substantially vertical outer sidewall of the annular spacer 472 adjoins a top surface of the annular spacer 472, and the annular spacer 472 can have a second periphery PR2 at which a substantially vertical inner sidewall of the annular spacer 472 adjoins a convex bottom surface of the annular spacer 472. The annular spacer 472 has a substantially vertical upper outer surface and a convex lower outer surface.
Referring to
Referring to
Referring to
Referring to
A combination of a sacrificial pillar structure 3A and at least one etch stop material portion is formed in each first memory opening. The at least one etch stop material portion can be embodied as an annular spacer 272, and/or can be embodied as a fill material portion 3B.
Referring to
The fill material portions 3B and the sacrificial pillar structures 3A are subsequently removed to form inter-stack memory openings 49 employing additional etch processes. The fill material portions 3B and the sacrificial pillar structures 3A are subsequently removed selective to the materials of the first alternating stack (132, 142), the second alternating stack (232, 242), the second insulating cap layer 270, and the annular spacers 272.
Subsequently, the processing steps of
The third exemplary structure can include a monolithic three-dimensional memory device, which can include: a first alternating stack of first insulating layers 132 and first electrically conductive layers 146 located over a top surface of a substrate 10; an insulating cap layer 170A overlying the first alternating stack (132, 146); a second alternating stack of second insulating layers 232 and second electrically conductive layers 246 overlying the insulating cap layer 170A; a memory stack structure 55 extending through the second alternating stack (232, 246), the insulating cap layer 170A, and the first alternating stack (132, 146) and comprising a semiconductor channel 60 and a memory film 50 including a plurality of charge storage regions; and an annular spacer 272 located within the insulating cap layer 170A and laterally surrounding the memory stack structure 55.
In one embodiment, the annular spacer 272 has a bottommost surface that is located above a horizontal plane including an interface between the first alternating stack (132, 146) and the first insulating cap layer 170A. In one embodiment, a substantially vertical outer sidewall of the annular spacer 272 can laterally protrude farther outward than any portion of the memory stack structure 55 within the first alternating stack (132, 146). In one embodiment, the annular spacer 272 can comprise a first periphery PR1 at which a substantially vertical outer sidewall of the annular spacer 272 adjoins a top surface of the annular spacer 272. In one embodiment, the annular spacer 272 can comprise a second periphery PR2 at which a substantially vertical inner sidewall of the annular spacer 272 adjoins a convex bottom surface of the annular spacer 272.
In one embodiment, the top surface of the annular spacer 272 can be a tapered convex surface adjoined to the substantially vertical inner sidewall of the annular spacer 272. In one embodiment, the annular spacer 272 can comprise a material selected from a doped semiconductor material and a dielectric material.
Referring to
Etch stop material portions 3C can be formed by depositing a material that can be employed as an etch stop material during subsequent formation of second memory openings. In one embodiment, the etch stop material having portions 3C can be formed by depositing a second semiconductor material a greater dopant concentration than the first semiconductor material of the sacrificial pillar structures 3A. In one embodiment, the second semiconductor material can be boron-doped silicon (e.g., boron doped amorphous silicon). A combination of a sacrificial pillar structure 3A and an etch stop material portion 3C is formed in each first memory opening. Each etch stop material portion 3C can fill the entire volume of a recess region 169.
Referring to
Referring to
Another anisotropic etch process can be performed to remove regions of the etch stop material portions 3C that underlie the second memory openings 221. Each remaining portion of the etch stop material portions 3C can constitute an annular spacer 372.
Referring to
Referring to
Referring to
Referring to
Referring to
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Referring to
Referring to
Referring to
Referring to
Each of the fourth and fifth exemplary structures or alternative embodiments thereof can include a monolithic three-dimensional memory device. The monolithic three-dimensional memory device can include a first alternating stack of first insulating layers 132 and first electrically conductive layers 146 located over a top surface of a substrate 10; an insulating cap layer 170A overlying the first alternating stack (132, 146); a second alternating stack of second insulating layers 232 and second electrically conductive layers 246 overlying the insulating cap layer 170A; a memory stack structure 55 extending through the second alternating stack (232, 246), the insulating cap layer 170A, and the first alternating stack (132, 146) and comprising a semiconductor channel 60 and a memory film 50 including a plurality of charge storage regions; and an annular spacer 372 located within the insulating cap layer 170A and laterally surrounding the memory stack structure 55.
In one embodiment, the annular spacer 372 has a planar top surface that contacts a bottommost layer within the second alternating stack (232, 246). In one embodiment, the annular spacer 372 has a bottommost surface that is located above a horizontal plane including an interface between the first alternating stack (132, 146) and the insulating cap layer 170A.
In one embodiment, a substantially vertical outer sidewall of the annular spacer 372 laterally protrudes farther outward than any portion of the memory stack structure 55 within the first alternating stack (132, 146) as illustrated in
In one embodiment, a substantially vertical outer sidewall of the annular spacer 372 is vertically coincident with a portion of the memory stack structure 55 within the first alternating stack (132, 146) located directly underneath the annular spacer 372 as illustrated in
In one embodiment, a bottom surface of the annular spacer 372 contacts a portion (e.g., a horizontal portion) of the memory stack structure 55 within the first alternating stack (132, 146) located directly underneath the annular spacer 372 within a horizontal plane as illustrated in
In one embodiment, the annular spacer 372 comprises a first periphery PR1 at which a substantially vertical outer sidewall of the annular spacer 372 adjoins a top surface of the annular spacer 372; and a second periphery PR2 at which a substantially vertical inner sidewall of the annular spacer adjoins a convex bottom surface of the annular spacer 372 as illustrated in
In one embodiment, the annular spacer 372 comprises a material selected from a doped semiconductor material and a dielectric material.
Each of the monolithic three-dimensional memory structures of the present disclosure can comprise a monolithic three-dimensional NAND memory device. The first and second electrically conductive layers can comprise, or can be electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device. The substrate 10 can comprise a silicon substrate. The monolithic three-dimensional NAND memory device can comprise an array of monolithic three-dimensional NAND strings over the silicon substrate. At least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings can be located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate can contain an integrated circuit comprising a driver circuit for the memory device located thereon. The array of monolithic three-dimensional NAND strings can comprises a plurality of semiconductor channels. At least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate. The array of monolithic three-dimensional NAND strings can comprises a plurality of charge storage elements. Each charge storage element can be located adjacent to a respective one of the plurality of semiconductor channels. The array of monolithic three-dimensional NAND strings can comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate. The plurality of control gate electrodes can comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.
The embodiments of the present disclosure reduce or prevent etching damage during the anisotropic etch of the horizontal surface of the bottom of the memory stack structure 55 at the interface of opening 121 and the epitaxial channel portion 11. In other words, the damage to the portions of the first semiconductor channel layer 601 and the memory film 50 located adjacent to layer 170A between the lower 121 and upper 221 openings is reduced or avoided during the anisotropic etch of the first semiconductor channel layer 601 and the memory films 50 to remove the horizontal bottom portion of each memory film 50 from the bottom of each memory opening before the step of forming the second semiconductor channel layer 602 in contact with the epitaxial channel portions 11. The damage to the portion of the structure 55 located adjacent to layer 170A between the lower 121 and upper 221 openings is reduced or avoided by not having an exposed horizontal portion of the memory stack structure 55 (i.e., horizontal shoulder portion of the first semiconductor channel layer 601) located adjacent to layer 170A between lower 121 and upper 221 openings during the anisotropic etch the bottom portion of the memory film 50. In one embodiment, the thicker tapered (i.e., non-horizontal) portion of the structure 55 is formed adjacent to layer 170A, as shown in
Therefore, in the above described embodiment, the step of anisotropically etching a horizontal bottom portion of the memory film 50 and the first semiconductor channel layer 601 such that damage to portions of the first semiconductor channel layer and the memory film located adjacent to the insulating cap layer 170A is reduced or avoided comprises not having a horizontal portion of the first semiconductor channel layer 601 located adjacent to the insulating cap layer 170A exposed in the inter-stack memory opening 49.
In one embodiment, not having a horizontal portion of the first semiconductor channel layer located adjacent to the insulating cap layer exposed in the inter-stack memory opening comprises forming a tapered non-horizontal portion of the first semiconductor channel layer 601 adjacent to the insulating cap layer 170A, as shown in
In another embodiment, not having a horizontal portion of the first semiconductor channel layer located adjacent to the insulating cap layer exposed in the inter-stack memory opening comprises forming an annular spacer 372 or 472 in the first memory opening 121 and forming substantially vertical memory stack structure 55 adjacent to annular spacer, as shown in
In another embodiment, not having a horizontal portion of the first semiconductor channel layer located adjacent to the insulating cap layer exposed in the inter-stack memory opening comprises forming a protective etch stop annular spacer 372 in the first memory opening 121 which covers the horizontal portion of the first semiconductor channel 601 in the inter-stack memory opening 49.
Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
Claims
1-33. (canceled)
34. A monolithic three-dimensional memory device, comprising: wherein:
- a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate;
- an insulating cap layer overlying the first alternating stack;
- a second alternating stack of second insulating layers and second electrically conductive layers overlying the insulating cap layer; and
- a memory stack structure extending through the second alternating stack, the insulating cap layer, and the first alternating stack and comprising a semiconductor channel and a memory film including a plurality of charge storage regions,
- the insulating cap layer comprises a first concave surface having a first radius of curvature, laterally surrounding the memory stack structure, and adjoined to an upper periphery of a substantially vertical sidewall of the memory stack structure; and
- the insulating cap layer comprises a second concave surface having a second radius of curvature that is greater than the first radius of curvature, laterally surrounding the memory stack structure, and adjoined to an upper periphery of the first concave surface
35. The monolithic three-dimensional memory device of claim 34, wherein the memory stacks structure contains a tapered portion adjacent to the insulating cap layer.
36. The monolithic three-dimensional memory device of claim 34, wherein:
- an upper periphery of the second concave surface is adjoined to a lower periphery of a substantially vertical sidewall of the insulating cap layer;
- a first convex sidewall of the memory stack structure contacts the first concave sidewall of the insulating cap layer; and
- a second convex sidewall of the memory stack structure contacts the second concave sidewall of the insulating cap layer.
37. The monolithic three-dimensional memory device of claim 34, further comprising an annular spacer that laterally surrounds the memory stack structure, wherein:
- a first convex sidewall of the annular spacer contacts the first concave sidewall of the insulating cap layer; and
- a second convex sidewall of the annular spacer contacts the second concave sidewall of the insulating cap layer.
Type: Application
Filed: Jun 15, 2016
Publication Date: Sep 21, 2017
Inventors: Masanori TSUTSUMI (Yokkaichi), Kota FUNAYAMA (Yokkaichi), Ryoichi EHARA (Yokkaichi), Youko FURIHATA (Yokkaichi), Zhenyu LU (Milpitas, CA), Tong ZHANG (Palo Alto, CA), Tadashi NAKAMURA (Yokkaichi)
Application Number: 15/183,195
