Patents by Inventor Masao Moriguchi
Masao Moriguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10965242Abstract: A photovoltaic apparatus includes: a power generation part; an angle changeable mechanism configured to support the power generation part so as to be able to change an elevation of the power generation part; a post configured to support the power generation part and the angle changeable mechanism; and a hinge mechanism configured to support the post so as to be able to change an angle of the post relative to an installation surface for the photovoltaic apparatus.Type: GrantFiled: June 2, 2016Date of Patent: March 30, 2021Assignee: Sumitomo Electric Industries, Ltd.Inventors: Koji Mori, Takashi Iwasaki, Masao Moriguchi
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Patent number: 10812010Abstract: A mounting structure for a photovoltaic module, the photovoltaic module including: a plurality of power generating elements; and a housing having a metal bottom plate on which the plurality of power generating elements are arrayed, and a resin side wall frame standing along an outer edge of the bottom plate, the mounting structure including: a support plate having a support face configured to be in contact with an outer face of the bottom plate to support the photovoltaic module; a washer to be disposed on one face which is an inner face of the bottom plate or a face, of the support plate, at a side opposite to the support face; and a rivet having a shank portion and a head, the shank portion being configured to be passed through the support plate and the bottom plate to be inserted into the washer, the head formed at one end portion of the shank portion, the rivet being configured to sandwich and fasten the support plate and the bottom plate between the washer and the head by an other end portion of the shanType: GrantFiled: July 10, 2017Date of Patent: October 20, 2020Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kenji Saito, Kazumasa Toya, Koji Mori, Masao Moriguchi, Hiroyuki Konaka
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Publication number: 20190238086Abstract: A mounting structure for a photovoltaic module, the photovoltaic module including: a plurality of power generating elements; and a housing having a metal bottom plate on which the plurality of power generating elements are arrayed, and a resin side wall frame standing along an outer edge of the bottom plate, the mounting structure including: a support plate having a support face configured to be in contact with an outer face of the bottom plate to support the photovoltaic module; a washer to be disposed on one face which is an inner face of the bottom plate or a face, of the support plate, at a side opposite to the support face; and a rivet having a shank portion and a head, the shank portion being configured to be passed through the support plate and the bottom plate to be inserted into the washer, the head formed at one end portion of the shank portion, the rivet being configured to sandwich and fasten the support plate and the bottom plate between the washer and the head by an other end portion of the shanType: ApplicationFiled: July 10, 2017Publication date: August 1, 2019Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kenji SAITO, Kazumasa TOYA, Koji MORI, Masao MORIGUCHI, Hiroyuki KONAKA
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Publication number: 20180294766Abstract: A photovoltaic apparatus includes: a power generation part; an angle changeable mechanism configured to support the power generation part so as to be able to change an elevation of the power generation part; a post configured to support the power generation part and the angle changeable mechanism; and a hinge mechanism configured to support the post so as to be able to change an angle of the post relative to an installation surface for the photovoltaic apparatus.Type: ApplicationFiled: June 2, 2016Publication date: October 11, 2018Inventors: Koji Mori, Takashi Iwasaki, Masao Moriguchi
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Publication number: 20170179162Abstract: A semiconductor device (100) according to the present invention is a semiconductor device with a thin-film transistor (10), and includes: a gate electrode (62) which has been formed on a substrate (60) as a part of the thin-film transistor (10); a gate insulating layer (66) which has been formed on the gate electrode (62); an oxide semiconductor layer (68) which has been formed on the gate insulating layer (66); a source electrode (70s) and a drain electrode (70d) which have been formed on the oxide semiconductor layer (68); a protective layer (72) which has been formed on the oxide semiconductor layer (68), the source electrode (70s) and the drain electrode (70d); an oxygen supplying layer (74) which has been formed on the protective layer (72); and an anti-diffusion layer (78) which has been formed on the oxygen supplying layer (74).Type: ApplicationFiled: March 3, 2017Publication date: June 22, 2017Inventors: Masao MORIGUCHI, Yohsuke KANZAKI, Yudai TAKANISHI, Takatsugu KUSUMI, Hiroshi MATSUKIZONO
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Patent number: 9377644Abstract: A TFT 1 is formed on a glass substrate 11, and a flattening resin film 17 covering the TFT 1 is formed. Furthermore, a moisture-proof protective film 18 covering the entire surface of the flattening resin film 17 is formed. For the protective film 18, a SiO2 film, a SiN film, a SiON film, or a stacked film thereof is used. The edge surfaces of the flattening resin film 17 are disposed on the inner side of or under a seal 4, and are formed in a tapered shape. By this, the entry of moisture into the flattening resin film 17 is prevented, preventing display degradation. This effect becomes noticeable in a display device including an oxide semiconductor TFT.Type: GrantFiled: March 16, 2012Date of Patent: June 28, 2016Assignee: SHARP KABUSHIKI KAISHAInventors: Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi, Takatsugu Kusumi
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Patent number: 9190526Abstract: A thin film transistor includes a gate electrode (11a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (13a) made of an oxide semiconductor and provided on the gate insulating film (12a), a source electrode (16aa) and a drain electrode (16ab) provided on the semiconductor layer (13a) via easily reducible metal layers (15aa, 15ab) and spaced apart from each other, with a channel region (C) interposed therebetween, a conductive region (E) provided in the semiconductor layer (13a), and a diffusion reducing portion (13ca, 13cb) provided in the semiconductor layer (13a), for reducing diffusion of the conductive region (E) into the channel region (C).Type: GrantFiled: April 12, 2012Date of Patent: November 17, 2015Assignee: Sharp Kabushiki KaishaInventors: Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi, Takatsugu Kusumi
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Publication number: 20150108467Abstract: A semiconductor device (100) according to the present invention is a semiconductor device with a thin-film transistor (10), and includes: a gate electrode (62) which has been formed on a substrate (60) as a part of the thin-film transistor (10); a gate insulating layer (66) which has been formed on the gate electrode (62); an oxide semiconductor layer (68) which has been formed on the gate insulating layer (66); a source electrode (70s) and a drain electrode (70d) which have been formed on the oxide semiconductor layer (68); a protective layer (72) which has been formed on the oxide semiconductor layer (68), the source electrode (70s) and the drain electrode (70d); an oxygen supplying layer (74) which has been formed on the protective layer (72); and an anti-diffusion layer (78) which has been formed on the oxygen supplying layer (74).Type: ApplicationFiled: December 15, 2011Publication date: April 23, 2015Applicant: SHARP KABUSHIKI KAISHAInventors: Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi, Takatsugu Kusumi, Hiroshi Matsukizono
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Patent number: 8957418Abstract: A semiconductor device according to the present invention includes: a gate electrode (62) of a thin film transistor (10) and an oxygen supply layer (64), the gate electrode (62) and the oxygen supply layer (64) being formed on a substrate (60); a gate insulating layer (66) formed on the gate electrode (62) and the oxygen supply layer (64); an oxide semiconductor layer (68) of the thin film transistor (10), the oxide semiconductor layer (68) being formed on the gate insulating layer (66); and a source electrode (70S) and a drain electrode (70d) of the thin film transistor (10), the source electrode (70S) and the drain electrode (70d) being formed on the gate insulating layer (66) and the oxide semiconductor layer (68).Type: GrantFiled: December 6, 2011Date of Patent: February 17, 2015Assignee: Sharp Kabushiki KaishaInventors: Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi, Takatsugu Kusumi, Hiroshi Matsukizono
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Patent number: 8900914Abstract: A method of manufacturing a TFT substrate includes: forming a gate electrode (12) and a gate insulating film (30) on a substrate (8); forming a source electrode (14) and a drain electrode (15) at a gap from each other on the gate insulating film (30), and forming a drain connection part (16); forming, after the step of forming the source electrode and the drain electrode, an oxide semiconductor layer (18, 18a, 18b) that contains a channel portion connecting the source electrode (14) to the drain electrode (15) and that contains an additional portion (18a) covering the drain connection part (16); oxidizing a surface of the oxide semiconductor layer (18, 18a, 18b); forming a contact hole (22) in an insulating film (32) that covers the oxide semiconductor layer; removing a portion of the additional portion (18a) of the oxide semiconductor layer that is located inside the contact hole (22); and forming a conductive layer (20) that electrically connects the drain connection part (16) that has been exposed.Type: GrantFiled: May 29, 2012Date of Patent: December 2, 2014Assignee: Sharp Kabushiki KaishaInventors: Yudai Takanishi, Masao Moriguchi, Yohsuke Kanzaki, Takatsugu Kusumi
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Patent number: 8884297Abstract: A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.Type: GrantFiled: May 6, 2011Date of Patent: November 11, 2014Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Sachiaki Tezuka, Yasuhiro Jinbo, Toshinari Sasaki, Hidekazu Miyairi, Yosuke Kanzaki, Masao Moriguchi
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Patent number: 8779478Abstract: A TFT 20 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a source electrode 24, a drain electrode 25, etc. The semiconductor layer 23 is comprised of a metal oxide semiconductor (IGZO), and has a source portion 23a that contacts the source electrode 24, a drain electrode 23b that contacts the drain electrode 25, and a channel portion 23c that is located between the source and drain portions 23a, 23b. A reduced region 30 is formed at least in the channel portion 23c of the semiconductor layer 23, and the reduced region 30 has a higher content of a simple substance of a metal such as In than the remaining portion of the semiconductor layer 23.Type: GrantFiled: May 23, 2011Date of Patent: July 15, 2014Assignee: Sharp Kabushiki KaishaInventors: Masao Moriguchi, Michiko Takei, Yohsuke Kanzaki, Tsuyoshi Inoue, Tetsuo Fukaya, Yudai Takanishi, Takatsugu Kusumi, Yoshiki Nakatani, Tetsuya Okamoto, Kenji Nakanishi
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Publication number: 20140110249Abstract: The purpose of the present invention is to provide a sputtering target with which a film having excellent characteristics can be obtained. A sputtering target (100) is constituted of a plurality of target members (10), a backing plate (20), a bonding agent (30), and protective members (50). The plurality of target members (10) and the backing plate (20) are bonded to each other with the bonding agent (30) therebetween. On a backing plate (20) surface that corresponds in position to gaps (15) between adjacent target members (10), grooves (40) are formed. Each of the grooves (40) is provided with the protective members (50), which are composed of the same material as that of the target members (10). The width (W2) of the protective members (50) is greater than the width (W1) of the gaps (15), and is less than the width (W3) of the grooves (40). The thickness (T4) of the protective members (50) is larger than the depth (D1) of the grooves (40).Type: ApplicationFiled: February 24, 2012Publication date: April 24, 2014Applicant: Sharp Kabushiki KaishaInventors: Yohsuke Kanzaki, Takatsugu Kusumi, Naohiro Tamari, Masao Moriguchi
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Publication number: 20140103342Abstract: A method of manufacturing a TFT substrate includes: forming a gate electrode (12) and a gate insulating film (30) on a substrate (8); forming a source electrode (14) and a drain electrode (15) at a gap from each other on the gate insulating film (30), and forming a drain connection part (16); forming, after the step of forming the source electrode and the drain electrode, an oxide semiconductor layer (18, 18a, 18b) that contains a channel portion connecting the source electrode (14) to the drain electrode (15) and that contains an additional portion (18a) covering the drain connection part (16); oxidizing a surface of the oxide semiconductor layer (18, 18a, 18b); forming a contact hole (22) in an insulating film (32) that covers the oxide semiconductor layer; removing a portion of the additional portion (18a) of the oxide semiconductor layer that is located inside the contact hole (22); and forming a conductive layer (20) that electrically connects the drain connection part (16) that has been exposed.Type: ApplicationFiled: May 29, 2012Publication date: April 17, 2014Applicant: SHARP KABUSHIKI KAISHAInventors: Yudai Takanishi, Masao Moriguchi, Yohsuke Kanzaki, Takatsugu Kusumi
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Patent number: 8686528Abstract: A semiconductor device of the present invention includes: a lower electrode (110); a contact layer (130) including a first contact layer (132), a second contact layer (134) and a third contact layer (136) overlapping with a semiconductor layer (120); and an upper electrode (140) including a first upper electrode (142), a second upper electrode (144) and a third upper electrode (146). The second contact layer (134) includes a first region (134a), and a second region (134b) separate from the first region (134a), and the second upper electrode (144) is directly in contact with the semiconductor layer (120) in a region between the first region (134a) and the second region (134b) of the second contact layer (134).Type: GrantFiled: January 29, 2010Date of Patent: April 1, 2014Assignee: Sharp Kabushiki KaishaInventors: Yudai Takanishi, Masao Moriguchi
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Publication number: 20140034947Abstract: A thin film transistor includes a gate electrode (11a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (13a) made of an oxide semiconductor and provided on the gate insulating film (12a), a source electrode (16aa) and a drain electrode (16ab) provided on the semiconductor layer (13a) via easily reducible metal layers (15aa, 15ab) and spaced apart from each other, with a channel region (C) interposed therebetween, a conductive region (E) provided in the semiconductor layer (13a), and a diffusion reducing portion (13ca, 13cb) provided in the semiconductor layer (13a), for reducing diffusion of the conductive region (E) into the channel region (C).Type: ApplicationFiled: April 12, 2012Publication date: February 6, 2014Applicant: SHARP KABUSHIKI KAISHAInventors: Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi, Takatsugu Kusumi
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Publication number: 20140009706Abstract: A TFT 1 is formed on a glass substrate 11, and a flattening resin film 17 covering the TFT 1 is formed. Furthermore, a moisture-proof protective film 18 covering the entire surface of the flattening resin film 17 is formed. For the protective film 18, a SiO2 film, a SiN film, a SiON film, or a stacked film thereof is used. The edge surfaces of the flattening resin film 17 are disposed on the inner side of or under a seal 4, and are formed in a tapered shape. By this, the entry of moisture into the flattening resin film 17 is prevented, preventing display degradation. This effect becomes noticeable in a display device including an oxide semiconductor TFT.Type: ApplicationFiled: March 16, 2012Publication date: January 9, 2014Applicant: SHARP KABUSHIKI KAISHAInventors: Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi, Takatsugu Kusumi
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Patent number: 8614493Abstract: A photosensor element is provided with a gate electrode disposed on an insulating substrate, a gate insulating film disposed so as to cover the gate electrode, a semiconductor layer disposed on the gate insulating film so as to overlap the gate electrode, and a source electrode and a drain electrode provided on the semiconductor layer so as to overlap the gate electrode and so as to face each other. The photosensor element has the semiconductor layer provided with an intrinsic semiconductor layer in which a channel region is defined and an extrinsic semiconductor layer that is laminated on the intrinsic semiconductor layer such that the channel region is exposed. The extrinsic semiconductor layer protrudes from the drain electrode on the side close to the channel region.Type: GrantFiled: November 11, 2010Date of Patent: December 24, 2013Assignee: Sharp Kabushiki KaishaInventors: Masao Moriguchi, Yohsuke Kanzaki, Tsuyoshi Inoue
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Patent number: D813800Type: GrantFiled: September 15, 2016Date of Patent: March 27, 2018Assignee: Sumitomo Electric Industries, Ltd.Inventors: Koji Mori, Takashi Iwasaki, Masao Moriguchi, Yoshiya Abiko
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Patent number: D851583Type: GrantFiled: September 6, 2017Date of Patent: June 18, 2019Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kenji Saito, Kazushi Iyatani, Hiroyuki Konaka, Masao Moriguchi, Koji Mori