Patents by Inventor Masao Moriguchi
Masao Moriguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080318390Abstract: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.Type: ApplicationFiled: August 12, 2008Publication date: December 25, 2008Applicant: Sharp Kabushiki KaishaInventors: Yasumori Fukushima, Masao Moriguchi, Yutaka Takafuji
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Patent number: 7425475Abstract: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.Type: GrantFiled: August 9, 2005Date of Patent: September 16, 2008Assignee: Sharp Kabushiki KaishaInventors: Yasumori Fukushima, Masao Moriguchi, Yutaka Takafuji
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Publication number: 20080164483Abstract: An active matrix substrate includes a glass substrate, a driver portion formed on the glass substrate in a protruding state, a stepped portion formed along a surface of the driver portion and a surface of the glass substrate, an insulating reentrant-angle compensating film formed on a surface of the stepped portion, for compensating for at least a part of a reentrant-angle shape of the stepped portion, and a wiring layer formed along a surface of the reentrant-angle compensating film and connected to the driver portion.Type: ApplicationFiled: March 9, 2006Publication date: July 10, 2008Inventors: Kazuhide Tomiyasu, Yutaka Takafuji, Masao Moriguchi
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Publication number: 20080149928Abstract: The present invention provides a production method of a semiconductor device, which can improve characteristics of a semiconductor element including a single crystal semiconductor layer formed by transferring on an insulating substrate. The present invention is a production method of a semiconductor device comprising a single crystal semiconductor layer formed on an insulating substrate, the production method comprising the steps of: implanting a substance for separation into a single crystal semiconductor substrate, thereby forming a separation layer; transferring a part of the single crystal semiconductor substrate, separated at the separation layer, onto the insulating substrate, thereby forming the single crystal semiconductor layer; forming a hydrogen-containing layer on at least one side of the single crystal semiconductor layer; and diffusing hydrogen from the hydrogen-containing layer to the single crystal semiconductor layer.Type: ApplicationFiled: January 17, 2006Publication date: June 26, 2008Inventors: Masao Moriguchi, Yutaka Takafuji, Steven Roy Droes
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Publication number: 20080128807Abstract: In fabricating a semiconductor device, an element forming surface formation step of forming a plurality of element forming surfaces of different heights on a semiconductor layer to have different levels, a semiconductor element formation step of forming a plurality of semiconductor elements and, one in each of a corresponding number of regions of the semiconductor layer, each region including an associated one of the plurality of element forming surfaces, a level-difference compensation insulating film formation step of forming a level-difference compensation insulating film on the semiconductor layer to cover the semiconductor elements and have a surface with different levels along the element forming surfaces, a release layer formation step of forming a release layer in the semiconductor layer by ion-implanting a peeling material through the level-difference compensation insulating film into the semiconductor layer, and a separation step of separating part of the semiconductor layer along the release layerType: ApplicationFiled: November 15, 2005Publication date: June 5, 2008Inventors: Yasumori Fukushima, Yutaka Takafuji, Masao Moriguchi
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Patent number: 7256109Abstract: A high-quality isotropic polycrystalline silicon (poly-Si) and a method for fabricating high quality isotropic poly-Si film are provided. The method includes forming a film of amorphous silicon (a-Si) and using a MISPC process to form poly-Si film in a first area of the a-Si film. The method then anneals a second area, included in the first area, using a Laser-Induced Lateral Growth (LILaC) process. In some aspects, a 2N-shot laser irradiation process is used as the LILaC process. In some aspects, a directional solidification process is used as the LILaC process. In response to using the MISPC film as a precursor film, the method forms low angle grain boundaries in poly-Si in the second area.Type: GrantFiled: April 4, 2005Date of Patent: August 14, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: Masao Moriguchi, Apostolos T. Voutsas, Mark A. Crowder
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Publication number: 20070122998Abstract: A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming a blocking mask over selected circuit areas; implanting H in the Si substrate; annealing; removing the blocking mask; in response to the H implanting, forming a cleaving plane in the Si substrate; bonding the circuit the top oxide layer to the carrier substrate; and, cleaving the Si substrate. More specifically, the cleaving plane is formed along a horizontal peak concentration (Rp) H layer in the Si substrate and along the buried oxide layer interface.Type: ApplicationFiled: January 26, 2007Publication date: May 31, 2007Inventors: Steve Droes, Masao Moriguchi, Yutaka Takafuji
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Patent number: 7179719Abstract: A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming a blocking mask over selected circuit areas; implanting H in the Si substrate; annealing; removing the blocking mask; in response to the H implanting, forming a cleaving plane in the Si substrate; bonding the circuit the top oxide layer to the carrier substrate; and, cleaving the Si substrate. More specifically, the cleaving plane is formed along a horizontal peak concentration (Rp) H layer in the Si substrate and along the buried oxide layer interface.Type: GrantFiled: September 28, 2004Date of Patent: February 20, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: Steve Droes, Masao Moriguchi, Yutaka Takafuji
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Publication number: 20060068565Abstract: A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming a blocking mask over selected circuit areas; implanting H in the Si substrate; annealing; removing the blocking mask; in response to the H implanting, forming a cleaving plane in the Si substrate; bonding the circuit the top oxide layer to the carrier substrate; and, cleaving the Si substrate. More specifically, the cleaving plane is formed along a horizontal peak concentration (Rp) H layer in the Si substrate and along the buried oxide layer interface.Type: ApplicationFiled: September 28, 2004Publication date: March 30, 2006Inventors: Steve Droes, Masao Moriguchi, Yutaka Takafuji
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Publication number: 20060043485Abstract: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.Type: ApplicationFiled: August 9, 2005Publication date: March 2, 2006Applicant: Sharp Kabushiki KaishaInventors: Yasumori Fukushima, Masao Moriguchi, Yutaka Takafuji
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Publication number: 20050245046Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.Type: ApplicationFiled: March 23, 2005Publication date: November 3, 2005Applicant: Sharp Kabushiki KaishaInventors: Yutaka Takafuji, Yasumori Fukushima, Masao Moriguchi
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Publication number: 20050236626Abstract: In a semiconductor device including an insulative substrate and a thin film device formed thereon, a thin film transistor having a non-single crystalline silicon thin film and a transistor having a single crystalline silicon thin film are intermixed, and a gate electrode film of the thin film transistor having single crystalline silicon is made of a material including a metal whose mass number is larger than that of silicon or a compound containing the metal.Type: ApplicationFiled: March 24, 2005Publication date: October 27, 2005Applicant: Sharp Kabushiki KaishaInventors: Yutaka Takafuji, Takashi Itoga, Steven Droes, Masao Moriguchi
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Patent number: 6939754Abstract: A high-quality isotropic polycrystalline silicon (poly-Si) and a method for fabricating high quality isotropic poly-Si film are provided. The method includes forming a film of amorphous silicon (a-Si) and using a MISPC process to form poly-Si film in a first area of the a-Si film. The method then anneals a second area, included in the first area, using a Laser-Induced Lateral Growth (LILaC) process. In some aspects, a 2N-shot laser irradiation process is used as the LILaC process. In some aspects, a directional solidification process is used as the LILaC process. In response to using the MISPC film as a precursor film, the method forms low angle grain boundaries in poly-Si in the second area.Type: GrantFiled: August 13, 2003Date of Patent: September 6, 2005Assignee: Sharp Laboratories of America, Inc.Inventors: Masao Moriguchi, Apostolos T. Voutsas, Mark A. Crowder
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Patent number: 6927107Abstract: In a production method of a semiconductor device, a catalyst element, e.g. Ni, is added to an amorphous silicon film, formed on a substrate with an insulating surface, for promoting crystallization of the amorphous silicon film. Thereafter, the amorphous silicon film is subjected to heat treatment to cause crystal growth therein. Next, the crystal growth is stopped in a state where minute amorphous regions (uncrystallized regions) remain in the film. Next, the silicon film is irradiated with strong light (laser light) so as to be further crystallized. As a result, a crystalline silicon film that has high quality and is excellent in uniformity is obtained.Type: GrantFiled: September 22, 2000Date of Patent: August 9, 2005Assignee: Sharp Kabushiki KaishaInventors: Naoki Makita, Hiromi Sakamoto, Masao Moriguchi
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Publication number: 20050170568Abstract: A high-quality isotropic polycrystalline silicon (poly-Si) and a method for fabricating high quality isotropic poly-Si film are provided. The method includes forming a film of amorphous silicon (a-Si) and using a MISPC process to form poly-Si film in a first area of the a-Si film. The method then anneals a second area, included in the first area, using a Laser-Induced Lateral Growth (LILaC) process. In some aspects, a 2N-shot laser irradiation process is used as the LILaC process. In some aspects, a directional solidification process is used as the LILaC process. In response to using the MISPC film as a precursor film, the method forms low angle grain boundaries in poly-Si in the second area.Type: ApplicationFiled: April 4, 2005Publication date: August 4, 2005Inventors: Masao Moriguchi, Apostolos Voutsas, Mark Crowder
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Publication number: 20050037551Abstract: A high-quality isotropic polycrystalline silicon (poly-Si) and a method for fabricating high quality isotropic poly-Si film are provided. The method includes forming a film of amorphous silicon (a-Si) and using a MISPC process to form poly-Si film in a first area of the a-Si film. The method then anneals a second area, included in the first area, using a Laser-Induced Lateral Growth (LILaC) process. In some aspects, a 2N-shot laser irradiation process is used as the LILaC process. In some aspects, a directional solidification process is used as the LILaC process. In response to using the MISPC film as a precursor film, the method forms low angle grain boundaries in poly-Si in the second area.Type: ApplicationFiled: August 13, 2003Publication date: February 17, 2005Inventors: Masao Moriguchi, Apostolos Voutsas, Mark Crowder
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Publication number: 20040258930Abstract: A polycrystalline silicon film with quasi-single crystal silicon in a selected region and a method for fabricating the polycrystalline silicon film are provided. The method comprises forming a film of amorphous silicon and using a 2N-shot process to form polycrystalline silicon in an area of the film. For 2N-shot process iterations, a laser beam is projected through aperture patterns to anneal the area. The laser forms two orthogonal groups of laser beamlets, causing two orthogonal groups of grain boundary to form in the area. The spacing within the groups is in a range of 0.1 microns (&mgr;m) to 100 &mgr;m. A directional solidification (DS) process projects a laser through an aperture pattern to sequentially anneal a portion of the area in a selected direction. The DS process smoothes grain boundary ridges and selectively removes grain boundaries.Type: ApplicationFiled: June 23, 2003Publication date: December 23, 2004Applicant: Sharp Laboratories of America Inc.Inventors: Masao Moriguchi, Apostolos T. Voutsas
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Patent number: 6770515Abstract: A TFT 123 formed on a glass substrate 101 has a crystalline silicon film 108 that serves as an active region. The crystalline silicon film 108 is formed by forming an a-Si film 103 containing hydrogen on the glass substrate 101, thereafter adding nickel 104 to the surface of the a-Si film 103 and subjecting the a-Si film 103 to which the nickel 104 has been added to heat treatment. The crystal grain size of each crystal of the crystalline silicon film 108 is smaller than the size of the channel region of a TFT 123. With this arrangement, a high-performance semiconductor device that has stable characteristics with little characteristic variation and a high integration density and is simply fabricated with high yield can be provided.Type: GrantFiled: September 12, 2000Date of Patent: August 3, 2004Assignee: Sharp Kabushiki KaishaInventors: Naoki Makita, Masao Moriguchi
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Patent number: 6607971Abstract: A method for an efficient extended pulse laser annealing process is provided. The method comprises: supplying a substrate with a thickness; selecting an energy density; selecting an extended pulse duration; laser annealing a substrate region; in response to cooling the substrate region, crystallizing the substrate region; and, efficiently extending the lateral growth of crystals in the substrate region. When the substrate has a thickness of approximately 300 Å, the energy density is selected to be in the range of 400 to 500 millijoules pre square centimeter (mJ/cm2). The pulse duration is selected to be in the range between 70 and 120 nanoseconds (ns). More preferably, the pulse duration is selected to be in the range between 90 and 120 ns. Most preferable, the pulse duration is approximately 100 ns. Then, efficiently extending the lateral growth of crystals in the substrate region includes laterally growing crystals at a rate of approximately 0.029 microns per nanosecond.Type: GrantFiled: April 30, 2002Date of Patent: August 19, 2003Assignee: Sharp Laboratories of America, Inc.Inventors: Masao Moriguchi, Apostolos T. Voutsas, Yasuhiro Mitani