Abstract: Disclosed is a photosensor element that is provided with a gate electrode (11da) disposed on an insulating substrate (10), a gate insulation film (12) disposed so as to cover the gate electrode (11da), a semiconductor layer (15db) disposed on the gate insulating film (12) so as to overlap the gate electrode (11da), and a source electrode (16da) and a drain electrode (16db) provided on the semiconductor layer (15db) so as to overlap the gate electrode (11da) and so as to face each other. The semiconductor layer (15db) is provided with an intrinsic semiconductor layer (13db) in which a channel region (C) is defined and an extrinsic semiconductor layer (14db) that is laminated on the intrinsic semiconductor layer (13db) such that the channel region (C) is exposed therefrom. The intrinsic semiconductor layer (13db) is an amorphous silicon layer containing nanocrystalline silicon particles.

Abstract: A diode 201 includes a gate electrode 2, a gate insulating layer 5 provided on the gate electrode 2, at least one semiconductor layer 6, 7 provided on the gate insulating layer 5 and which includes a first region 6a and a second region 7b, a first electrode 10 which is provided on the first region 6a and which is electrically coupled to the first region 6a and the gate electrode 2, and a second electrode 12 which is provided on the second region 7b and which is electrically coupled to the second region 7b. The at least one semiconductor layer 6, 7 includes a channel region 6c which extends above the gate electrode 2 with the intervention of the gate insulating layer 5 therebetween, and a resistor region 7d which does not extend above the gate electrode 2. When the diode 201 is in an ON state, an electric current path is formed between the first electrode 10 and the second electrode 12, the electric current path including the channel region 6c and the resistor region 7d.

Abstract: A semiconductor device according to the present invention includes: a gate electrode (62) of a thin film transistor (10) and an oxygen supply layer (64), the gate electrode (62) and the oxygen supply layer (64) being formed on a substrate (60); a gate insulating layer (66) formed on the gate electrode (62) and the oxygen supply layer (64); an oxide semiconductor layer (68) of the thin film transistor (10), the oxide semiconductor layer (68) being formed on the gate insulating layer (66); and a source electrode (70S) and a drain electrode (70d) of the thin film transistor (10), the source electrode (70S) and the drain electrode (70d) being formed on the gate insulating layer (66) and the oxide semiconductor layer (68).

Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.

Abstract: The present invention aims at reducing an OFF current in a thin film transistor while maintaining an ON-state current. A TFT (100) includes a glass substrate (101) formed thereon with a source electrode (110) and a drain electrode (112) having their respective upper surfaces formed with n-type silicon layers (120, 121) of microcrystalline silicon. Microcrystalline silicon regions (135, 136) are formed respectively on the n-type silicon layers (120, 121) while an amorphous silicon region (130) is formed on the glass substrate (101), and these are covered by a microcrystalline silicon layer (145). Therefore, ON-state current flows from the drain electrode (112), through the microcrystalline silicon region (135), the microcrystalline silicon layer (145) and the microcrystalline silicon region (136) in this order, and then to the source electrode (110). Also, OFF current is limited by the amorphous silicon region (130).

Abstract: A TFT 20 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a source electrode 24, a drain electrode 25, etc. The semiconductor layer 23 is comprised of a metal oxide semiconductor (IGZO), and has a source portion 23a that contacts the source electrode 24, a drain electrode 23b that contacts the drain electrode 25, and a channel portion 23c that is located between the source and drain portions 23a, 23b. A reduced region 30 is formed at least in the channel portion 23c of the semiconductor layer 23, and the reduced region 30 has a higher content of a simple substance of a metal such as In than the remaining portion of the semiconductor layer 23.

Abstract: An object is to provide a manufacturing method of a microcrystalline silicon film with improved adhesion between an insulating film and the microcrystalline silicon film. The microcrystalline silicon film is formed in the following manner. Over an insulating film, a microcrystalline silicon grain having a height that allows the microcrystalline silicon grain to be completely oxidized by later plasma oxidation (e.g., a height greater than 0 nm and less than or equal to 5 nm), or a microcrystalline silicon film or an amorphous silicon film having a thickness that allows the microcrystalline silicon film or the amorphous silicon film to be completely oxidized by later plasma oxidation (e.g., a thickness greater than 0 nm and less than or equal to 5 nm) is formed.

Abstract: A semiconductor device 10 according to the present invention includes an active layer 14 supported on a substrate 11 and having two channel regions 14c1, 14c2, a source region 14s, a drain region 14d, and an intermediate region 14m formed between the two channel regions 14c1, 14c2; a contact layer 16 having a source contact region 16s, a drain contact region 16d, and an intermediate contact region 16m; a source electrode 18s; a drain electrode 18d; an intermediate electrode 18m; and a gate electrode 12 facing the two channel regions and the intermediate region through a gate insulating film 13 interposed therebetween. An entire portion of the intermediate electrode 18m that is located between the first channel region 14c1 and the second channel region 14c2 overlaps the gate electrode 12 through the intermediate region 14m and the gate insulating film 13.

Abstract: A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.

Abstract: A semiconductor device 101 includes: a substrate 1; an active layer 4 provided on the substrate 1 and including a channel region 4c, and a first region 4a and a second region 4b that are respectively located on opposite sides of the channel region 4c; first and second contact layers 6a and 6b respectively in contact with the first and second regions 4a and 4b of the active layer 4; a first electrode 7 electrically coupled to the first region 4a via the first contact layer 6a; a second electrode 8 electrically coupled to the second region 4b via the second contact layer 6b; and a gate electrode 2 provided such that a gate insulating layer 3 is interposed between the gate electrode 2 and the active layer 4, the gate electrode 2 being configured to control a conductivity of the channel region 4c. The active layer 4 contains silicon. The semiconductor device further includes an oxygen-containing silicon layer 5 between the active layer 4 and the first and second contact layers 6a, 6b.

Abstract: In an inverted staggered type TFT (100), contact layers (150a and 150b) that electrically connect a channel layer (140) to source and drain electrodes (160a and 160b), respectively, include n+ amorphous silicon layers (151a and 151b), n+ microcrystalline silicon layers (152a and 152b), and n+ microcrystalline silicon layers (153a and 153b). The n+ microcrystalline silicon layers (152a and 152b) have a lower crystallization rate than the n+ microcrystalline silicon layers (153a and 153b) and are formed between the n+ amorphous silicon layers (151a and 151b) and the n+ microcrystalline silicon layers (153a and 153b). In this case, since the film thickness of incubation layers formed on surfaces of the n+ amorphous silicon layers (151a and 151b) decreases, the resistance value of the contact layers (150a and 150b) decreases. By this, the contact resistance of the TFT (100) decreases and the mobility can be increased.

Abstract: A method for manufacturing a semiconductor device includes: a first step of forming a base layer, which includes an element portion having a gate electrode and a flat interlayer insulating film formed so as to cover the gate electrode; a second step of ion implanting a delamination material into the base layer to form a delamination layer; a third step of bonding the base layer to a substrate; and a fourth step of separating and removing a part of the base layer along the delamination layer. An implantation depth of the delamination material in the gate electrode is substantially the same as that of the delamination material in the interlayer insulating film.

Abstract: Disclosed is a photosensor element that is provided with a gate electrode (11da) disposed on an insulating substrate (10), a gate insulation film (12) disposed so as to cover the gate electrode (11da), a semiconductor layer (15db) disposed on the gate insulating film (12) so as to overlap the gate electrode (11da), and a source electrode (16da) and a drain electrode (16db) provided on the semiconductor layer (15db) so as to overlap the gate electrode (11da) and so as to face each other. The semiconductor layer (15db) is provided with an intrinsic semiconductor layer (13db) in which a channel region (C) is defined and an extrinsic semiconductor layer (14db) that is laminated on the intrinsic semiconductor layer (13db) such that the channel region (C) is exposed therefrom. The intrinsic semiconductor layer (13db) is an amorphous silicon layer containing nanocrystalline silicon particles.

Abstract: A photosensor element (6a) is provided with a gate electrode (11da) disposed on an insulating substrate (10), a gate insulating film (12) disposed so as to cover the gate electrode (11da), a semiconductor layer (15db) disposed on the gate insulating film (12) so as to overlap the gate electrode (11da), and a source electrode (16da) and a drain electrode (16db) provided on the semiconductor layer (15db) so as to overlap the gate electrode (11da) and so as to face each other. The photosensor element (6a) has the semiconductor layer (15db) provided with an intrinsic semiconductor layer (13db) in which a channel region (C) is defined and an extrinsic semiconductor layer (14db) that is laminated on the intrinsic semiconductor layer (13db) such that the channel region (C) is exposed. The extrinsic semiconductor layer (14db) protrudes from the drain electrode (16db) on the side close to the channel region (C).

Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.

Abstract: The present invention aims at reducing an OFF current in a thin film transistor while maintaining an ON-state current. A TFT (100) includes a glass substrate (101) formed thereon with a source electrode (110) and a drain electrode (112) having their respective upper surfaces formed with n-type silicon layers (120, 121) of microcrystalline silicon. Microcrystalline silicon regions (135, 136) are formed respectively on the n-type silicon layers (120, 121) while an amorphous silicon region (130) is formed on the glass substrate (101), and these are covered by a microcrystalline silicon layer (145). Therefore, ON-state current flows from the drain electrode (112), through the microcrystalline silicon region (135), the microcrystalline silicon layer (145) and the microcrystalline silicon region (136) in this order, and then to the source electrode (110). Also, OFF current is limited by the amorphous silicon region (130).

Abstract: A semiconductor device includes a semiconductor layer having a channel region, an impurity layer having a source region and a drain region, and a gate electrode provided so as to face the semiconductor layer with a gate insulating film interposed therebetween. The semiconductor layer has a layered structure of at least a first amorphous film and a crystalline film including a crystal phase, and the first amorphous film is formed directly on the gate insulating film.

Abstract: An object of the present invention is to provide a thin film transistor having a gate insulating film for suppressing a shift amount of a threshold voltage generated by use under a high temperature environment. In a thin film transistor having a channel layer made of microcrystalline silicon, a gate insulating film 140 is a film obtained by laminating a first silicon nitride film 141 having a nitrogen concentration of 6×1021 atoms/cc or less and a second silicon nitride film 142 having a nitrogen concentration higher than 6×1021 atoms/cc. Therefore, the second silicon nitride film 142 increases the blocking effect against mobile ions entering from a glass substrate 20 to make the mobile ions less likely to be stored in an interface with a channel layer 50. The first silicon nitride film 141 increases the dielectric breakdown voltage of the gate insulating film 140.

Abstract: A semiconductor device 100 according to the present invention includes a TFT 120 and a TFT 140. The TFT 120 has a gate electrode 122, a semiconductor layer 130 including a microcrystalline semiconductor film 132, and a gate insulating layer 124 provided between the gate electrode 122 and the semiconductor layer 130. The TFT 140 has a gate electrode 142, a semiconductor layer 150 including a microcrystalline semiconductor film 152, and a gate insulating layer 144 provided between the gate electrode 142 and the semiconductor layer 150. The thickness and layer structure of the semiconductor layer 150 of the TFT 140 are different from those of the semiconductor layer 130 of the TFT 120.

Abstract: Disclosed is a semiconductor device provided with the following: an active layer 6 formed on a substrate 1 having a channel region 6c, a first region 6a located on one side of the channel region 6c, and a second region 6b located on the other side of the channel region 6c; a contact formation layer 8 that is formed on the active layer 6 and that has a separation region 9, a first contact region 8a, and a second contact region 8b, the latter two of which are located on the first region 6a and the second region 6b of the active layer, respectively; a first electrode 10 electrically connected to the first region 6a through the first contact region 8a; a second electrode 11 electrically connected to the second region 6b through the second contact region 8b; and a gate electrode 2 provided with respect to the active layer 6 through a gate insulating layer 4.