Patents by Inventor Masao Shingu

Masao Shingu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210210507
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Application
    Filed: March 18, 2021
    Publication date: July 8, 2021
    Inventors: Masaaki HIGUCHI, Masaru Kito, Masao Shingu
  • Patent number: 10985173
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: April 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaaki Higuchi, Masaru Kito, Masao Shingu
  • Patent number: 10269821
    Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masao Shingu, Katsuyuki Sekine, Hirokazu Ishigaki, Makoto Fujiwara
  • Patent number: 10181477
    Abstract: According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hirokazu Ishigaki, Tatsuya Okamoto, Masao Shingu
  • Patent number: 10121797
    Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: November 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigeki Kobayashi, Satoshi Konagai, Atsushi Konno, Kenta Yamada, Masaaki Higuchi, Masao Shingu, Soichiro Kitazaki, Yoshimasa Mikajiri
  • Patent number: 10032935
    Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 24, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masaaki Higuchi, Masao Shingu, Tatsuya Kato, Takeshi Murata, Makoto Fujiwara, Masaki Kondo, Muneyuki Tsuda, Takashi Kurusu
  • Publication number: 20180175057
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Application
    Filed: February 15, 2018
    Publication date: June 21, 2018
    Inventors: Masaaki HIGUCHI, Masaru KITO, Masao SHINGU
  • Patent number: 9929176
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaaki Higuchi, Masaru Kito, Masao Shingu
  • Patent number: 9831180
    Abstract: According to the embodiment, the semiconductor device includes: a substrate; a stacked body; and a plurality of columnar portions. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a stacked portion and a staircase portion. The plurality of electrode layers includes a first portion and a second portion. The columnar portions are provided in the stacked portion of the stacked body. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body extending in the stacking direction and a charge storage film. The second portion includes a third portion. A thickness of the third portion along the stacking direction is thinner than a thickness of the first portion along the stacking direction.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: November 28, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masao Shingu, Kenta Yamada, Masaaki Higuchi, Daigo Ichinose
  • Patent number: 9786678
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: October 10, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuyuki Sekine, Masaaki Higuchi, Masao Shingu, Hirokazu Ishigaki, Naoki Yasuda
  • Publication number: 20170271527
    Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.
    Type: Application
    Filed: September 29, 2016
    Publication date: September 21, 2017
    Inventors: Masaaki HIGUCHI, Masao SHINGU, Tatsuya KATO, Takeshi MURATA, Makoto FUJIWARA, Masaki KONDO, Muneyuki TSUDA, Takashi KURUSU
  • Publication number: 20170263633
    Abstract: According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar.
    Type: Application
    Filed: September 12, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu ISHIGAKI, Tatsuya Okamoto, Masao Shingu
  • Publication number: 20170263558
    Abstract: According to the embodiment, the semiconductor device includes: a substrate; a stacked body; and a plurality of columnar portions. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a stacked portion and a staircase portion. The plurality of electrode layers includes a first portion and a second portion. The columnar portions are provided in the stacked portion of the stacked body. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body extending in the stacking direction and a charge storage film. The second portion includes a third portion. A thickness of the third portion along the stacking direction is thinner than a thickness of the first portion along the stacking direction.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masao Shingu, Kenta Yamada, Masaaki Higuchi, Daigo Ichinose
  • Publication number: 20170243873
    Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.
    Type: Application
    Filed: September 19, 2016
    Publication date: August 24, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki KOBAYASHI, Satoshi KONAGAI, Atsushi KONNO, Kenta YAMADA, Masaaki HIGUCHI, Masao SHINGU, Soichiro KITAZAKI, Yoshimasa MIKAJIRI
  • Publication number: 20170117293
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Application
    Filed: January 4, 2017
    Publication date: April 27, 2017
    Inventors: Masaaki HIGUCHI, Masaru KITO, Masao SHINGU
  • Patent number: 9620653
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
  • Publication number: 20170062451
    Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.
    Type: Application
    Filed: February 17, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masao SHINGU, Katsuyuki SEKINE, Hirokazu ISHIGAKI, Makoto FUJIWARA
  • Patent number: 9583504
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Grant
    Filed: March 2, 2014
    Date of Patent: February 28, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki Higuchi, Masaru Kito, Masao Shingu
  • Patent number: 9379320
    Abstract: According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: June 28, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Shingu, Akira Takashima, Koichi Muraoka
  • Publication number: 20160104802
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
    Type: Application
    Filed: December 16, 2015
    Publication date: April 14, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masao SHINGU, Jun FUJIKI, Naoki YASUDA, Koichi MURAOKA