Patents by Inventor Masao Shingu
Masao Shingu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140021528Abstract: A semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO2, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths Lcharge, Ltop, and Lgate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “Lcharge<Ltop and Lgate<Ltop”.Type: ApplicationFiled: July 18, 2013Publication date: January 23, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Masao Shingu, Akira Takashima, Koichi Muraoka
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Publication number: 20140001536Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: ApplicationFiled: August 30, 2013Publication date: January 2, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masao SHINGU, Jun FUJIKI, Naoki YASUDA, Koichi MURAOKA
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Publication number: 20130343122Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: ApplicationFiled: August 30, 2013Publication date: December 26, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masao SHINGU, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Patent number: 8569823Abstract: According to one embodiment, a semiconductor device includes a semiconductor region, a tunnel insulating film provided on the semiconductor region, a charge storage insulating film provided on the tunnel insulating film and having a hafnium oxide including a cubic region, a block insulating film provided on the charge storage insulating film, and a control gate electrode provided on the block insulating film.Type: GrantFiled: September 19, 2011Date of Patent: October 29, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Masao Shingu, Shosuke Fujii, Akira Takashima, Daisuke Matsushita, Jun Fujiki, Naoki Yasuda, Yasushi Nakasaki, Koichi Muraoka
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Patent number: 8558301Abstract: There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures.Type: GrantFiled: August 12, 2011Date of Patent: October 15, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masao Shingu, Akira Takashima, Koichi Muraoka
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Publication number: 20130234222Abstract: A semiconductor memory device includes a substrate, a structure body, a semiconductor layer, and a memory film. The memory film is provided between the semiconductor layer and the plurality of electrode films. The memory film includes a charge storage film, a block film, and a tunnel film. The block film is provided between the charge storage film and the plurality of electrode films. The tunnel film is provided between the charge storage film and the semiconductor layer. The tunnel film includes a first film containing silicon oxide, a second film containing silicon oxide, and a third film provided between the first film and the second film and containing silicon oxynitride. When a composition of the silicon oxynitride contained in the third film is expressed by a ratio x of silicon oxide and a ratio (1?x) of silicon nitride, 0.5?x<1 holdes.Type: ApplicationFiled: August 30, 2012Publication date: September 12, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Naoki YASUDA, Masaaki Higuchi, Katsuyuki Sekine, Masao Shingu
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Patent number: 8482053Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a source region and a drain region provided on a surface area of a semiconductor region, a tunnel insulating film provided on a channel between the source region and the drain region, a charge storage layer provided on the tunnel insulating film, a first dielectric film provided on the charge storage layer and containing lanthanum aluminum silicon oxide or oxynitride, a second dielectric film provided on the first dielectric film and containing oxide or oxynitride containing at least one of hafnium (Hf), zirconium (Zr), titanium (Ti), and a rare earth metal, and a control gate electrode provided on the second dielectric film.Type: GrantFiled: August 5, 2011Date of Patent: July 9, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Masao Shingu, Koichi Muraoka
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Publication number: 20130134372Abstract: According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.Type: ApplicationFiled: November 29, 2012Publication date: May 30, 2013Inventors: Kiwamu SAKUMA, Haruka KUSAI, Shosuke FUJII, Li ZHANG, Masahiro KIYOTOSHI, Masao SHINGU
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Patent number: 8390054Abstract: According to one embodiment, a semiconductor memory element includes a semiconductor layer, a tunnel insulator provided on the semiconductor layer, a charge accumulation film provided on the tunnel insulator having a film thickness of 0.9 nm or more and 2.8 nm or less and the charge accumulation film containing cubic HfO2 particles, a block insulator provided on the charge accumulation film, and a control electrode provided on the block insulator.Type: GrantFiled: September 13, 2010Date of Patent: March 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Daisuke Matsushita, Yasushi Nakasaki, Masao Shingu
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Publication number: 20130010535Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masao SHINGU, Jun FUJIKI, Naoki YASUDA, Koichi MURAOKA
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Patent number: 8294195Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: GrantFiled: October 13, 2011Date of Patent: October 23, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Publication number: 20120193597Abstract: According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.Type: ApplicationFiled: January 31, 2012Publication date: August 2, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Masao SHINGU, Akira Takashima, Koichi Muraoka
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Patent number: 8193577Abstract: A nonvolatile semiconductor memory device includes a source region and a drain region provided apart from each other in a semiconductor substrate, a first insulating film provided on a channel region between the source region and the drain region, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer and including a stacked structure of a lanthanum aluminum silicate film and a dielectric film made of silicon oxide or silicon oxynitride, and a control gate electrode provided on the second insulating film.Type: GrantFiled: July 21, 2009Date of Patent: June 5, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Masao Shingu, Naoki Yasuda, Koichi Muraoka
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Publication number: 20120068250Abstract: According to one embodiment, a semiconductor device includes a semiconductor region, a tunnel insulating film provided on the semiconductor region, a charge storage insulating film provided on the tunnel insulating film and having a hafnium oxide including a cubic region, a block insulating film provided on the charge storage insulating film, and a control gate electrode provided on the block insulating film.Type: ApplicationFiled: September 19, 2011Publication date: March 22, 2012Inventors: Tsunehiro Ino, Masao Shingu, Shosuke Fujii, Akira Takashima, Daisuke Matsushita, Jun Fujiki, Naoki Yasuda, Yasushi Nakasaki, Koichi Muraoka
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Publication number: 20120032248Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: ApplicationFiled: October 13, 2011Publication date: February 9, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masao SHINGU, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Publication number: 20120025297Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a source region and a drain region provided on a surface area of a semiconductor region, a tunnel insulating film provided on a channel between the source region and the drain region, a charge storage layer provided on the tunnel insulating film, a first dielectric film provided on the charge storage layer and containing lanthanum aluminum silicon oxide or oxynitride, a second dielectric film provided on the first dielectric film and containing oxide or oxynitride containing at least one of hafnium (Hf), zirconium (Zr), titanium (Ti), and a rare earth metal, and a control gate electrode provided on the second dielectric film.Type: ApplicationFiled: August 5, 2011Publication date: February 2, 2012Inventors: Akira TAKASHIMA, Masao SHINGU, Koichi MURAOKA
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Publication number: 20120025294Abstract: There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures.Type: ApplicationFiled: August 12, 2011Publication date: February 2, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masao SHINGU, Akira Takashima, Koichi Muraoka
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Patent number: 8058681Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: GrantFiled: March 17, 2009Date of Patent: November 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Publication number: 20110241101Abstract: According to one embodiment, a semiconductor memory element includes a semiconductor layer, a tunnel insulator provided on the semiconductor layer, a charge accumulation film provided on the tunnel insulator having a film thickness of 0.9 nm or more and 2.8 nm or less and the charge accumulation film containing cubic HfO2 particles, a block insulator provided on the charge accumulation film, and a control electrode provided on the block insulator.Type: ApplicationFiled: September 13, 2010Publication date: October 6, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsunehiro INO, Daisuke MATSUSHITA, Yasushi NAKASAKI, Masao SHINGU
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Patent number: 7956405Abstract: A semiconductor storage element includes: a source region and a drain region provided in a semiconductor substrate; a tunnel insulating film provided on the semiconductor substrate between the source region and the drain region; a charge storage film provided on the tunnel insulating film; a block insulating film provided on the charge storage film; a gate electrode provided on the block insulating film; and a region containing a gas molecule, the region provided in a neighborhood of an interface between the charge storage film and the block insulating film.Type: GrantFiled: March 16, 2009Date of Patent: June 7, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Shosuke Fujii, Jun Fujiki, Akira Takashima, Masao Shingu, Daisuke Matsushita, Naoki Yasuda, Koichi Muraoka