Patents by Inventor Masaru Senoo

Masaru Senoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10700054
    Abstract: A semiconductor apparatus includes a semiconductor substrate provided with a plurality of diode ranges and a plurality of IGBT ranges. The IGBT ranges and the diode ranges are alternately arranged along a first direction in plan view of the semiconductor substrate along a thickness direction of the semiconductor substrate. Each diode range is provided with a plurality of n-type cathode regions and a plurality of p-type current-limiting regions in a range of being in contact with a lower electrode. The cathode regions and the current-limiting regions are alternately arranged along a second direction intersecting the first direction in each diode range. Each IGBT range is provided with a p-type collector region in a range of being in contact with the lower electrode. The collector region in each IGBT range is in contact with each cathode region in the adjacent diode range.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: June 30, 2020
    Assignee: DENSO CORPORATION
    Inventors: Masaru Senoo, Jun Okawara
  • Publication number: 20190287963
    Abstract: A semiconductor device may include a semiconductor substrate, a plurality of trenches, an insulating film, a control electrode, an upper electrode, and a lower electrode. A diode region of the semiconductor substrate may include an n-type bypass region being in direct contact with each insulating film and connected to the upper electrode, a p-type anode contact region connected to the upper electrode, a p-type body region disposed below the bypass region and the anode contact region and being in direct contact with each insulating film below the bypass region, an n-type drift region being in direct contact with each insulating film below the body region, and an n-type cathode region disposed below the drift region and connected to the lower electrode. A position of a lower end of the anode contact region may be located below a position of a lower end of the bypass region.
    Type: Application
    Filed: February 19, 2019
    Publication date: September 19, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keiichi KONDOH, Masaru SENOO, Hiroshi HOSOKAWA
  • Publication number: 20190214379
    Abstract: A semiconductor apparatus includes a semiconductor substrate provided with a plurality of diode ranges and a plurality of IGBT ranges. The IGBT ranges and the diode ranges are alternately arranged along a first direction in plan view of the semiconductor substrate along a thickness direction of the semiconductor substrate. Each diode range is provided with a plurality of n-type cathode regions and a plurality of p-type current-limiting regions in a range of being in contact with a lower electrode. The cathode regions and the current-limiting regions are alternately arranged along a second direction intersecting the first direction in each diode range. Each IGBT range is provided with a p-type collector region in a range of being in contact with the lower electrode. The collector region in each IGBT range is in contact with each cathode region in the adjacent diode range.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 11, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masaru Senoo, Jun Okawara
  • Patent number: 10256232
    Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode provided above the semiconductor substrate; a sense anode electrode provided above the semiconductor substrate; a resistance layer provided above the semiconductor substrate and having a resistivity higher than the sense anode electrode; a lower main electrode provided below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode comprises a first anode region of a p-type connected to the sense anode electrode via the resistance layer and a first cathode region of an n-type connected to the lower main electrode.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: April 9, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaru Senoo
  • Publication number: 20190051648
    Abstract: A diode includes a first-conductivity-type barrier region disposed between a drift region and a second impurity region and having an impurity concentration higher than that of the drift region and a second-conductivity-type field extension prevention region disposed between the barrier region and the drift region. The diode also includes a trench gate disposed to extend from a second main surface of a semiconductor substrate through the second impurity region and the barrier region and reach the field extension prevention region. The trench gate has a gate electrode for applying a gate voltage. A gate electrode is applied with a parasitic gate voltage, as the gate voltage. The parasitic gate voltage has an absolute value of a potential difference with a second electrode being equal to or greater than a threshold voltage of a parasitic transistor formed of the second impurity region, the barrier region, and the field extension prevention region.
    Type: Application
    Filed: December 19, 2016
    Publication date: February 14, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Noriyuki KAKIMOTO, Masaru SENOO
  • Patent number: 10163890
    Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: December 25, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masaru Senoo, Masanori Miyata
  • Publication number: 20180240795
    Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode provided above the semiconductor substrate; a sense anode electrode provided above the semiconductor substrate; a resistance layer provided above the semiconductor substrate and having a resistivity higher than the sense anode electrode; a lower main electrode provided below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode comprises a first anode region of a p-type connected to the sense anode electrode via the resistance layer and a first cathode region of an n-type connected to the lower main electrode.
    Type: Application
    Filed: January 10, 2018
    Publication date: August 23, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaru SENOO
  • Publication number: 20180240792
    Abstract: A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode.
    Type: Application
    Filed: January 11, 2018
    Publication date: August 23, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masaru SENOO, Masanori MIYATA
  • Patent number: 9865728
    Abstract: A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 9, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Masaru Senoo, Takashi Kuno, Satoshi Kuwano, Noriyuki Kakimoto, Toshitaka Kanemaru, Kenta Hashimoto, Yuma Kagata
  • Patent number: 9853024
    Abstract: A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a semiconductor substrate having a gate trench and a dummy trench. The semiconductor substrate includes emitter, body, barrier and pillar regions between the gate trench and the dummy trench. The emitter region is an n-type region being in contact with the gate insulating film and exposed on a front surface. The body region is a p-type region being in contact with the gate insulating film at a rear surface side of the emitter region. The barrier region is an n-type region being in contact with the gate insulating film at a rear surface side of the body region and in contact with the dummy insulating film. The pillar region is an n-type region connected to the front surface electrode and the barrier region.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: December 26, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masaru Senoo, Yasuhiro Hirabayashi
  • Patent number: 9786746
    Abstract: A semiconductor device includes a diode and a semiconductor substrate. The diode includes a p-type anode region and an n-type cathode region. A lifetime control layer is provided in an area within the cathode region. The area is located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate. The lifetime control layer has crystal defects which are distributed along a planar direction of the semiconductor substrate. A peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: October 10, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Masaru Senoo
  • Publication number: 20170263754
    Abstract: A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.
    Type: Application
    Filed: February 6, 2017
    Publication date: September 14, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka SOENO, Masaru SENOO, Takashi KUNO, Satoshi KUWANO, Noriyuki KAKIMOTO, Toshitaka KANEMARU, Kenta HASHIMOTO, Yuma KAGATA
  • Publication number: 20170250179
    Abstract: A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a semiconductor substrate having a gate trench and a dummy trench. The semiconductor substrate includes emitter, body, barrier and pillar regions between the gate trench and the dummy trench. The emitter region is an n-type region being in contact with the gate insulating film and exposed on a front surface. The body region is a p-type region being in contact with the gate insulating film at a rear surface side of the emitter region. The barrier region is an n-type region being in contact with the gate insulating film at a rear surface side of the body region and in contact with the dummy insulating film. The pillar region is an n-type region connected to the front surface electrode and the barrier region.
    Type: Application
    Filed: September 4, 2015
    Publication date: August 31, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masaru SENOO, Yasuhiro HIRABAYASHI
  • Patent number: 9691888
    Abstract: An IGBT includes a rectangular trench including first to fourth trenches and a gate electrode arranged inside of the rectangular trench. An n-type emitter region includes a first emitter region being in contact with the first trench, and a second emitter region being in contact with the third trench. A body contact region includes a first body contact region being in contact with the second trench, and a second body contact region being in contact with the fourth trench. A surface body region is in contact with the trenches in ranges from connection portions to the emitter regions.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: June 27, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun Okawara, Masaru Senoo
  • Publication number: 20170162681
    Abstract: An IGBT includes a rectangular trench including first to fourth trenches and a gate electrode arranged inside of the rectangular trench. An n-type emitter region includes a first emitter region being in contact with the first trench, and a second emitter region being in contact with the third trench. A body contact region includes a first body contact region being in contact with the second trench, and a second body contact region being in contact with the fourth trench. A surface body region is in contact with the trenches in ranges from connection portions to the emitter regions.
    Type: Application
    Filed: October 11, 2016
    Publication date: June 8, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun OKAWARA, Masaru SENOO
  • Patent number: 9666579
    Abstract: In a plan view of a semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region. In a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 30, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masaru Senoo, Akitaka Soeno, Yasuhiro Hirabayashi, Takashi Kuno, Yusuke Yamashita, Satoru Machida
  • Patent number: 9601592
    Abstract: An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: March 21, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masaru Senoo, Kyosuke Miyagi, Tsuyoshi Nishiwaki, Jun Saito
  • Patent number: 9595603
    Abstract: A semiconductor device includes a semiconductor layer and a trench gate portion that extends toward a deep portion from a front surface of the semiconductor layer. The semiconductor layer includes an island region surrounded by the trench gate portion. A first side surface of the trench gate portion and a second side surface of the trench gate portion are in contact with the island region. A first conductivity type contact region that includes a first contact region that is in contact with the first side surface and a second contact region that is in contact with the second side surface is provided in the island region. Moreover, a second conductivity type contact region that is in contact with the trench gate portion at a position between the first contact region and the second contact region is provided in the island region.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: March 14, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Yasuhiro Hirabayashi, Masaru Senoo, Akitaka Soeno, Satoru Machida, Yusuke Yamashita
  • Patent number: 9589952
    Abstract: A reverse conducting IGBT is provided with a trench gate member that is provided in an IGBT region and has a lattice-pattern layout, and a trench member that is provided in a diode region and has a stripe-pattern layout. The diode region of the semiconductor substrate includes an anode region of a first conductive type, a drift region of a second conductive type and a barrier region of the second conductive type. The barrier region is electrically connected to a top surface electrode via a pillar member that extends from a top surface of the semiconductor substrate.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: March 7, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaru Senoo
  • Publication number: 20170040442
    Abstract: An IGBT comprises emitter regions, a collector region, a drift region and a body region in a semiconductor substrate. The semiconductor substrate comprises a trench extending from the front surface of the semiconductor substrate and reaching the drill region. The trench partitions the front surface of the semiconductor substrate into a plurality of blocks in a plan view of the semiconductor substrate. The plurality of the blocks comprises cell blocks, each of which is partitioned to be smaller than a predetermined area by the trench, and a surrounding block which is a region other than the cell blocks. The collector region, the drift region, the body region and the emitter region are provided in each of the cell blocks and the surrounding block. A total area of the emitter regions in the cell blocks is greater than a total area of the emitter region in the surrounding block.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 9, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yasuhiro HIRABAYASHI, Masaru SENOO