Abstract: An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.

Abstract: A diode is provided with a pillar region formed so as to extend between a barrier region and an anode electrode, contact the barrier region, and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region; and a barrier height adjusting region formed so as to be located between the pillar region and the anode electrode, and contact the pillar region and the anode electrode. The barrier height adjusting region includes at least one component selected from the group consisting of a second conductivity type semiconductor having a concentration lower than that of an anode region, the first conductivity type semiconductor having a concentration lower than that of the pillar region, and an i-type semiconductor. The barrier height adjusting region and the anode electrode are connected through a Schottky junction.

Abstract: An object of the present application is to reduce the gate capacitance without lowering the withstand voltage of a semiconductor device and prevent generation of a leak current between main electrodes even when an oxide film is formed poorly. A semiconductor device of the present application comprises a gate electrode and a dummy gate electrode. The gate electrode is insulated from an emitter electrode and faces a part of a body region via an insulating film, the part of the body region separating a drift region and an emitter region from each other. The dummy gate electrode is electrically connected with the emitter electrode and is connected with the drift region and the body region via the insulating film. At least a part of the dummy gate electrode comprises a first conductive region of the same type as the drift region. In the dummy gate electrode, the emitter electrode is separated from the drift region by the first conductive region.

Abstract: A method for fabricating a semiconductor device in which a lifetime control region can be formed within a predetermined range with high positioning accuracy is provided. In a semiconductor device, an IGBT element region and a diode element region may be formed in one semiconductor substrate. The IGBT element region may include a second conductivity type drift layer and a first conductivity type body layer. The diode element region may include a second conductivity type drift layer and a first conductivity type anode layer. A concentration of heavy metal included in the drift layer of the diode element region may be set higher than a concentration of the heavy metal included in the drift layer of the IGBT element region.

Abstract: A technique for expanding an effective area in which a semiconductor structure required for a semiconductor device to function is desired. With the semiconductor device 2 of this invention, a pad 12 to be connected with a conductive wire 14 is sloping with respect to the surface of the semiconductor device 2 around the pad 12 and along a longitudinal direction of the conductive wire 14. Consequently, the length of the pad 12, when projecting the pad 12 onto the surface of the semiconductor device 2, can be shortened. As a result, the area of the pad region 10 can be reduced and the effective area for forming a semiconductor structure can be enlarged.

Abstract: A first semiconductor device comprising: a first conductivity type drift region formed in a semiconductor substrate; a second conductivity type body region formed at an upper surface of the semiconductor substrate on an upper surface side of the drift region; a first conductivity type first semiconductor region formed on a part of an upper surface of the body region; and a trench gate type insulated gate penetrating the first semiconductor region and the body region, and formed to a depth at which the insulated gate contacts the drift region. A part of the insulated gate on a drift region side relative to the body region is deeper at a center portion than at both end portions in a longitudinal direction of the insulated gate.

Abstract: A field plate of a semiconductor device is provided with i) an insulating film that is formed on a surface of the semiconductor substrate, and includes a plurality of first regions, one for each of a plurality of FLR layers, that contact the layers and are arranged at intervals in a radial direction, and a plurality of second regions, one for each of the first regions, that are adjacent to the first regions in the radial direction, and ii) a plurality of first conductive films that are formed, one for each of the layers, inside of the insulating film, are arranged at intervals in the radial direction along the layers when a semiconductor substrate is viewed from above, and that are electrically connected to the layers. A thickness of at least a portion of the second regions is thicker than a thickness of the first regions.

Abstract: This specification discloses a semiconductor device having higher electric strength. The semiconductor device disclosed in this specification has a semiconductor element region, a peripheral termination region, a peripheral electrode, an insulating film, and an intermediate electrode. A semiconductor element is formed within the semiconductor element region. The peripheral termination region is formed around the semiconductor element region and formed of a single conductive type semiconductor. The semiconductor element region and the peripheral termination region are exposed at one surface of a semiconductor substrate. The peripheral electrode is formed on a surface of the peripheral termination region and along a circumference of the semiconductor substrate. The insulating film is formed on the surface of the peripheral termination region and between the semiconductor element region and the peripheral electrode. The intermediate electrode is formed on the insulating film.

Abstract: A first semiconductor device comprising: a first conductivity type drift region formed in a semiconductor substrate; a second conductivity type body region formed at an upper surface of the semiconductor substrate on an upper surface side of the drift region; a first conductivity type first semiconductor region formed on a part of an upper surface of the body region; and a trench gate type insulated gate penetrating the first semiconductor region and the body region, and formed to a depth at which the insulated gate contacts the drift region. A part of the insulated gate on a drift region side relative to the body region is deeper at a center portion than at both end portions in a longitudinal direction of the insulated gate.

Abstract: A technology for a vertical semiconductor device having a RESURF structure, which is capable of preventing the drop of the withstand voltage when the adhesion of external electric charges occurs is provided. The vertical semiconductor device disclosed in the present specification has a cell region and a non-cell region disposed outside the cell region. This vertical semiconductor device has a diffusion layer disposed in at least part of the non-cell region. When the vertical semiconductor device is viewed in a plane, the diffusion layer has an impurity surface density higher than that satisfying a RESURF condition at an end part close to the cell region, and an impurity surface density lower than that satisfying the RESURF condition at an end part far from the cell region.

Abstract: A technique for expanding an effective area in which a semiconductor structure required for a semiconductor device to function is desired. With the semiconductor device 2 of this invention, a pad 12 to be connected with a conductive wire 14 is sloping with respect to the surface of the semiconductor device 2 around the pad 12 and along a longitudinal direction of the conductive wire 14. Consequently, the length of the pad 12, when projecting the pad 12 onto the surface of the semiconductor device 2, can be shortened. As a result, the area of the pad region 10 can be reduced and the effective area for forming a semiconductor structure can be enlarged.

Abstract: A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.

Abstract: An object of the present application is to reduce the gate capacitance without lowering the withstand voltage of a semiconductor device and prevent generation of a leak current between main electrodes even when an oxide film is formed poorly. A semiconductor device of the present application comprises a gate electrode and a dummy gate electrode. The gate electrode is insulated from an emitter electrode and faces a part of a body region via an insulating film, the part of the body region separating a drift region and an emitter region from each other. The dummy gate electrode is electrically connected with the emitter electrode and is connected with the drift region and the body region via the insulating film. At least a part of the dummy gate electrode comprises a first conductive region of the same type as the drift region. In the dummy gate electrode, the emitter electrode is separated from the drift region by the first conductive region.

Abstract: A collector region is not formed in at least a portion of an ineffective region where an insulating film is formed on a front face of an IGBT. In this portion in which the collector region is not formed, a collector electrode and a buffer layer contact each other. Since the buffer layer and the collector region differ from each other in conductivity type, no electric charge is introduced from the collector electrode into the buffer layer. Thus, introduction of electric charges into a drift region at a portion in the ineffective region is suppressed, which alleviates electric field concentration in a semiconductor substrate. Further, in the IGBT, the semiconductor substrate and the collector electrode contact each other and heat transfer to the collector electrode is not hindered even in the range where the collector region is not formed. Thus, concentration of heat generation in the semiconductor substrate is alleviated.

Abstract: A protective coating is formed on the surface of a semiconductor device. The surface is located on the side to which an extension portion of a wire connected to a pad of the semiconductor device is pulled. The protective coating is formed such that its height decreases toward the pad.

Abstract: The present teaching provides a semiconductor device capable of relaxing stress transferred to a contact region during wire bonding and improving reliability of wire bonding. A semiconductor device comprises contact regions, an interlayer insulating film, an emitter electrode, and a stress relaxation portion. The contact regions are provided at a certain interval in areas exposing at a surface of a semiconductor substrate. The interlayer insulating film is provided on the surface of the semiconductor substrate between adjacent contact regions. The emitter electrode is provided on an upper side of the semiconductor substrate and electrically connected to each of the contact regions. The stress relaxation portion is provided on an upper surface of the emitter electrode in an area only above the contact regions. The stress relaxation portion is formed of a conductive material.

Abstract: This specification discloses a semiconductor device having higher electric strength. The semiconductor device disclosed in this specification has a semiconductor element region, a peripheral termination region, a peripheral electrode, an insulating film, and an intermediate electrode. A semiconductor element is formed within the semiconductor element region. The peripheral termination region is formed around the semiconductor element region and formed of a single conductive type semiconductor. The semiconductor element region and the peripheral termination region are exposed at one surface of a semiconductor substrate. The peripheral electrode is formed on a surface of the peripheral termination region and along a circumference of the semiconductor substrate. The insulating film is formed on the surface of the peripheral termination region and between the semiconductor element region and the peripheral electrode. The intermediate electrode is formed on the insulating film.

Abstract: A collector region is not formed in at least a portion of an ineffective region where an insulating film is formed on a front face of an IGBT. In this portion in which the collector region is not formed, a collector electrode and a buffer layer contact each other. Since the buffer layer and the collector region differ from each other in conductivity type, no electric charge is introduced from the collector electrode into the buffer layer. Thus, introduction of electric charges into a drift region at a portion in the ineffective region is suppressed, which alleviates electric field concentration in a semiconductor substrate. Further, in the IGBT, the semiconductor substrate and the collector electrode contact each other and heat transfer to the collector electrode is not hindered even in the range where the collector region is not formed. Thus, concentration of heat generation in the semiconductor substrate is alleviated.

Abstract: A protective coating is formed on the surface of a semiconductor device. The surface is located on the side to which an extension portion of a wire connected to a pad of the semiconductor device is pulled. The protective coating is formed such that its height decreases toward the pad.

Abstract: A technique for expanding an effective area in which a semiconductor structure required for a semiconductor device to function is desired. With the semiconductor device 2 of this invention, a pad 12 to be connected with a conductive wire 14 is sloping with respect to the surface of the semiconductor device 2 around the pad 12 and along a longitudinal direction of the conductive wire 14. Consequently, the length of the pad 12, when projecting the pad 12 onto the surface of the semiconductor device 2, can be shortened. As a result, the area of the pad region 10 can be reduced and the effective area for forming a semiconductor structure can be enlarged.