Abstract: In a plan view of a semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region. In a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area.

Abstract: An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.

Abstract: A semiconductor device includes a semiconductor layer and a trench gate portion that extends toward a deep portion from a front surface of the semiconductor layer. The semiconductor layer includes an island region surrounded by the trench gate portion. A first side surface of the trench gate portion and a second side surface of the trench gate portion are in contact with the island region. A first conductivity type contact region that includes a first contact region that is in contact with the first side surface and a second contact region that is in contact with the second side surface is provided in the island region. Moreover, a second conductivity type contact region that is in contact with the trench gate portion at a position between the first contact region and the second contact region is provided in the island region.

Abstract: A reverse conducting IGBT is provided with a trench gate member that is provided in an IGBT region and has a lattice-pattern layout, and a trench member that is provided in a diode region and has a stripe-pattern layout. The diode region of the semiconductor substrate includes an anode region of a first conductive type, a drift region of a second conductive type and a barrier region of the second conductive type. The barrier region is electrically connected to a top surface electrode via a pillar member that extends from a top surface of the semiconductor substrate.

Abstract: An IGBT comprises emitter regions, a collector region, a drift region and a body region in a semiconductor substrate. The semiconductor substrate comprises a trench extending from the front surface of the semiconductor substrate and reaching the drill region. The trench partitions the front surface of the semiconductor substrate into a plurality of blocks in a plan view of the semiconductor substrate. The plurality of the blocks comprises cell blocks, each of which is partitioned to be smaller than a predetermined area by the trench, and a surrounding block which is a region other than the cell blocks. The collector region, the drift region, the body region and the emitter region are provided in each of the cell blocks and the surrounding block. A total area of the emitter regions in the cell blocks is greater than a total area of the emitter region in the surrounding block.

Abstract: A semiconductor device includes a semiconductor layer and a trench gate portion that extends toward a deep portion from a front surface of the semiconductor layer. The semiconductor layer includes an island region surrounded by the trench gate portion. A first side surface of the trench gate portion and a second side surface of the trench gate portion are in contact with the island region. A first conductivity type contact region that includes a first contact region that is in contact with the first side surface and a second contact region that is in contact with the second side surface is provided in the island region. Moreover, a second conductivity type contact region that is in contact with the trench gate portion at a position between the first contact region and the second contact region is provided in the island region.

Abstract: A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a drift region of a first conductive type, a body region of a second conductive type that is disposed above the drift region, and a barrier region of the first conductive type that is disposed in the body region and electrically connects to the emitter electrode via a pillar member which extends from the one of main surfaces of the semiconductor layer. The barrier region is not contact with a side surface of the insulated trench gate.

Abstract: A semiconductor apparatus includes a semiconductor substrate including a device region and a peripheral region. The peripheral region includes guard rings. A first peripheral insulating film, first peripheral conducting films, a second peripheral insulating film and second peripheral conducting films are laminated in the peripheral region. Each of the first peripheral conducting films extends annularly. Each of the second peripheral conducting films overlaps a part of the corresponding first peripheral conducting film. Each of the second peripheral conducting films is connected to the corresponding first peripheral conducting film via a first contact hole. Each of the second peripheral conducting films is connected to the corresponding guard ring via a second contact hole. A center of at least one of the second contact holes is located on inner side with respect to a center line of the guard ring in a width direction.

Abstract: A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a barrier region of the first conductive type, wherein the barrier region is disposed in the body region and electrically connects to the emitter electrode via a pillar member which extends from the one of main surfaces of the semiconductor layer. The barrier region includes a first barrier partial region, wherein a distance between the first barrier partial region and the drift region is a first distance, and a second barrier partial region, wherein a distance between the second barrier partial region and the drift region is a second distance which is longer than the first distance. The second barrier partial region is in contact with a side surface of an insulated trench gate.

Abstract: A semiconductor apparatus includes a semiconductor substrate including a device region and a peripheral region. The peripheral region includes guard rings. A first peripheral insulating film, first peripheral conducting films, a second peripheral insulating film and second peripheral conducting films are laminated in the peripheral region. Each of the first peripheral conducting films extends annularly. Each of the second peripheral conducting films overlaps a part of the corresponding first peripheral conducting film. Each of the second peripheral conducting films is connected to the corresponding first peripheral conducting film via a first contact hole. Each of the second peripheral conducting films is connected to the corresponding guard ring via a second contact hole. A center of at least one of the second contact holes is located on inner side with respect to a center line of the guard ring in a width direction.

Abstract: In a plan view of a semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region. In a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area.

Abstract: A reverse conducting IGBT is provided with a trench gate member that is provided in an IGBT region and has a lattice-pattern layout, and a trench member that is provided in a diode region and has a stripe-pattern layout. The diode region of the semiconductor substrate includes an anode region of a first conductive type, a drift region of a second conductive type and a barrier region of the second conductive type. The barrier region is electrically connected to a top surface electrode via a pillar member that extends from a top surface of the semiconductor substrate.

Abstract: A buffer layer includes an n+-type first buffer region and an n+-type second buffer region. The first buffer region is provided at a first depth from a first main surface of a semiconductor layer and has an impurity concentration higher than an impurity concentration of a drift layer. The second buffer region is provided at a second depth from the first main surface of the semiconductor layer and has an impurity concentration higher than the impurity concentration in the drift layer, the second depth being shallower than the first depth. The first buffer region delimits an opening in a plane of the semiconductor layer at the first depth. The second buffer region delimits an opening in a plane of the semiconductor layer at the second depth.

Abstract: A semiconductor device includes a diode and a semiconductor substrate. The diode includes a p-type anode region and an n-type cathode region. A lifetime control layer is provided in an area within the cathode region. The area is located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate. The lifetime control layer has crystal defects which are distributed along a planar direction of the semiconductor substrate. A peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.

Abstract: A semiconductor device is provided with a silicon layer, an upper surface side aluminum layer containing silicon and an insulation film. The upper surface side aluminum layer contacts and is layered on a part of a surface of the silicon layer. The insulation film contacts and is layered on another part of the surface of the silicon layer. The insulation film is adjacent to and contacts the upper surface side aluminum layer. The insulation film includes an insulation film body and a plurality of first nodule segregated portions projecting from the insulation film body toward the upper surface side aluminum layer as seen along a vertical direction relative to the surface of the silicon layer. A corner is formed by a side surface of the insulation film body and a side surface of each of the first nodule segregated portions as seen along the vertical direction.

Abstract: A technology for reducing contact resistance between a semiconductor substrate and an electrode is provided. A provided method for manufacturing a semiconductor device includes: forming an oxide film 62 on a surface 12b of a semiconductor substrate 12 by bringing the surface 12b into contact with ammonia-hydrogen peroxide water mixture; forming a groove 60 on the surface 12b by irradiating light to heat the surface 12b covered with the oxide film 62; removing the oxide film 62 to expose the surface 12b; and forming an electrode 16 on the exposed surface 12b.

Abstract: A semiconductor device has emitter regions disposed in at least one cell region in a first inter-trench region, not disposed in a middle inter-trench region, and disposed in at least one cell region in the second inter-trench region. Each of the emitter regions is disposed at a position that is not in contact with first trenches but is in contact with two second trenches defining the corresponding cell region.

Abstract: A switching circuit includes a wiring having a parallel circuit of a first IGBT and a second IGBT. If a current of the wiring is relatively large, both of the first and second IGBTs are turned on at a turn-on timing and turned off at a turn-off timing. If the current is relatively small, one of the first and second IGBTs is turned on at the turn-on timing and turned off at the turn-off timing, and the other is maintained in an off state from a timing preceding the turn-off timing until the turn-off timing.

Abstract: Provided is a semiconductor device in which movable ions in an insulation layer on a main surface are reduced and dielectric strength is enhanced. A semiconductor device has a plurality of FLRs, an insulation layer, and a semiconductor layer. The plurality of FLRs surrounds, in a plan view of a substrate, an active region in which an element is formed. The insulation layer is provided on the main surface of the semiconductor device and covers the plurality of FLRs. The semiconductor layer is provided in the insulation layer and surrounds the active region in parallel to the FLRs. The semiconductor layer contains impurities at a surface density lower than a surface density that satisfies a RESURF condition. In the plan view, the semiconductor layer overlaps with a part of the region (an inter-ring region) between adjacent FLRs and does not overlap with rest of the inter-ring region.

Abstract: A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a barrier region of the first conductive type, wherein the barrier region is disposed in the body region and electrically connects to the emitter electrode via a pillar member which extends from the one of main surfaces of the semiconductor layer. The barrier region includes a first barrier partial region, wherein a distance between the first barrier partial region and the drift region is a first distance, and a second barrier partial region, wherein a distance between the second barrier partial region and the drift region is a second distance which is longer than the first distance. The second barrier partial region is in contact with a side surface of an insulated trench gate.