Patents by Inventor Masashi Horiguchi
Masashi Horiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6504402Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: January 22, 2002Date of Patent: January 7, 2003Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
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Patent number: 6500715Abstract: The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units.Type: GrantFiled: May 11, 2001Date of Patent: December 31, 2002Assignee: Hitachi, Ltd.Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
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Patent number: 6498762Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.Type: GrantFiled: January 9, 2002Date of Patent: December 24, 2002Assignee: Hitachi, Ltd.Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
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Patent number: 6492719Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: GrantFiled: October 26, 2001Date of Patent: December 10, 2002Assignee: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
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Publication number: 20020163846Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instructions for the memory unit is provided, the data input buffer is rendered active in advance before the instructions for the write operation is provided, whereby wastefully consumed power is reduced.Type: ApplicationFiled: July 5, 2002Publication date: November 7, 2002Applicant: Hitachi, Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 6473354Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.Type: GrantFiled: January 9, 2002Date of Patent: October 29, 2002Assignee: Hitachi, Ltd.Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
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Publication number: 20020135397Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.Type: ApplicationFiled: March 25, 2002Publication date: September 26, 2002Inventors: Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi
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Publication number: 20020117742Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: ApplicationFiled: January 22, 2002Publication date: August 29, 2002Applicant: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
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Patent number: 6438014Abstract: A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each of the individual memory modules are connected in serial form, and each of the individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.Type: GrantFiled: March 12, 2001Date of Patent: August 20, 2002Assignee: Hitachi, Ltd.Inventors: Seiji Funaba, Yoshinobu Nakagome, Masashi Horiguchi, Yoji Nishio
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Publication number: 20020101755Abstract: A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each individual memory modules are connected in serial form, and each individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.Type: ApplicationFiled: March 26, 2002Publication date: August 1, 2002Inventors: Seiji Funaba, Yoshinobu Nakagome, Masashi Horiguchi, Yoji Nishio
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Patent number: 6424586Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.Type: GrantFiled: January 9, 2002Date of Patent: July 23, 2002Assignee: Hitachi, Ltd.Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
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Patent number: 6424590Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instructions for the memory unit is provided, the data input buffer is rendered active in advance before the instructions for the write operation is provided, whereby wastefully consumed power is reduced.Type: GrantFiled: December 21, 2001Date of Patent: July 23, 2002Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Publication number: 20020089051Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: ApplicationFiled: January 22, 2002Publication date: July 11, 2002Applicant: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
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Publication number: 20020084804Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: ApplicationFiled: January 22, 2002Publication date: July 4, 2002Applicant: Hitachi, Ltd.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
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Patent number: 6404239Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: July 10, 2000Date of Patent: June 11, 2002Assignee: Hitachi, Ltd.Inventors: Takayuki Kawahara, Ryoichi Hori, Masashi Horiguchi, Ryoichi Kurihara, Kiyoo Itoh, Masakazu Aoki, Takeshi Sakata, Kunio Uchiyama
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Patent number: 6396761Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.Type: GrantFiled: June 7, 2001Date of Patent: May 28, 2002Assignee: Hitachi, Ltd.Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
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Publication number: 20020060944Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.Type: ApplicationFiled: January 9, 2002Publication date: May 23, 2002Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
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Publication number: 20020057129Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.Type: ApplicationFiled: January 15, 2002Publication date: May 16, 2002Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
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Publication number: 20020057620Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.Type: ApplicationFiled: January 9, 2002Publication date: May 16, 2002Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
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Publication number: 20020057619Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an, operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.Type: ApplicationFiled: January 9, 2002Publication date: May 16, 2002Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata