Patents by Inventor Masashi Horiguchi
Masashi Horiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6291847Abstract: A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.Type: GrantFiled: September 24, 1998Date of Patent: September 18, 2001Assignee: Hitachi, Ltd.Inventors: Kiyonori Ohyu, Makoto Ohkura, Aritoshi Sugimoto, Yoshitaka Tadaki, Makoto Ogasawara, Masashi Horiguchi, Norio Hasegawa, Shinichi Fukada
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Patent number: 6281711Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: April 15, 1999Date of Patent: August 28, 2001Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
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Patent number: 6275440Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.Type: GrantFiled: December 5, 2000Date of Patent: August 14, 2001Assignee: Hitachi, Ltd.Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
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Patent number: 6270935Abstract: An exposed film package for preserving one strip of exposed photographic film includes a film sheath, which has plural pockets. Plural film pieces are formed by cutting the one strip of the exposed film, and contained respectively in the pockets in the film sheath. An index photograph is constituted of photographic paper, on which positive images of frames from the one strip of the exposed film are printed. The photographic paper has a size substantially equal to the film pieces. The positive images are formed in reducing a size of the frames, and grouped in association with the film pieces. Groups of the positive images are arranged in consideration of an order of exposure of the frames. The index photograph is contained in one of the pockets in association with the film pieces constituting the one strip.Type: GrantFiled: January 16, 2001Date of Patent: August 7, 2001Assignee: Fuji Photo Film Co., Ltd.Inventors: Setsuji Tatsumi, Kazuhiro Tagawa, Toru Kurokawa, Katsumi Otake, Masashi Horiguchi, Toru Tsuji
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Patent number: 6270932Abstract: An exposed film package for preserving one strip of exposed photographic film includes a film sheath, which has plural pockets. Plural film pieces are formed by cutting the one strip of the exposed film, and contained respectively in the pockets in the film sheath. An index photograph is constituted of photographic paper, on which positive images of frames from the one strip of the exposed film are printed. The photographic paper has a size substantially equal to the film pieces. The positive images are formed in reducing a size of the frames, and grouped in association with the film pieces. Groups of the positive images are arranged in consideration of an order of exposure of the frames. The index photograph is contained in one of the pockets in association with the film pieces constituting the one strip.Type: GrantFiled: January 16, 2001Date of Patent: August 7, 2001Assignee: Fuji Photo Film Co., Ltd.Inventors: Setsuji Tatsumi, Kazuhiro Tagawa, Toru Kurokawa, Katsumi Otake, Masashi Horiguchi, Toru Tsuji
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Patent number: 6268741Abstract: This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks.Type: GrantFiled: May 19, 2000Date of Patent: July 31, 2001Assignee: Hitachi, Ltd.Inventors: Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi
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Publication number: 20010008497Abstract: A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.Type: ApplicationFiled: January 16, 2001Publication date: July 19, 2001Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Publication number: 20010004218Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: ApplicationFiled: January 23, 2001Publication date: June 21, 2001Applicant: Hitachi, Ltd.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
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Patent number: 6240035Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.Type: GrantFiled: April 30, 1999Date of Patent: May 29, 2001Assignee: Hitachi, Ltd.Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
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Publication number: 20010001695Abstract: An exposed film package for preserving one strip of exposed photographic film includes a film sheath, which has plural pockets. Plural film pieces are formed by cutting the one strip of the exposed film, and contained respectively in the pockets in the film sheath. An index photograph is constituted of photographic paper, on which positive images of frames from the one strip of the exposed film are printed. The photographic paper has a size substantially equal to the film pieces. The positive images are formed in reducing a size of the frames, and grouped in association with the film pieces. Groups of the positive images are arranged in consideration of an order of exposure of the frames. The index photograph is contained in one of the pockets in association with the film pieces constituting the one strip.Type: ApplicationFiled: January 16, 2001Publication date: May 24, 2001Inventors: Setsuji Tatsumi, Kazuhiro Tagawa, Toru Kurokawa, Katsumi Otake, Masashi Horiguchi, Toru Tsuji
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Publication number: 20010001262Abstract: A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.Type: ApplicationFiled: January 16, 2001Publication date: May 17, 2001Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Publication number: 20010001289Abstract: An exposed film package for preserving one strip of exposed photographic film includes a film sheath, which has plural pockets. Plural film pieces are formed by cutting the one strip of the exposed film, and contained respectively in the pockets in the film sheath. An index photograph is constituted of photographic paper, on which positive images of frames from the one strip of the exposed film are printed. The photographic paper has a size substantially equal to the film pieces. The positive images are formed in reducing a size of the frames, and grouped in association with the film pieces. Groups of the positive images are arranged in consideration of an order of exposure of the frames. The index photograph is contained in one of the pockets in association with the film pieces constituting the one strip.Type: ApplicationFiled: January 16, 2001Publication date: May 17, 2001Inventors: Setsuji Tatsumi, Kazuhiro Tagawa, Toru Kurokawa, Katsumi Otake, Masashi Horiguchi, Toru Tsuji
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Publication number: 20010000133Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.Type: ApplicationFiled: December 5, 2000Publication date: April 5, 2001Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
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Patent number: 6212089Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.Type: GrantFiled: April 11, 2000Date of Patent: April 3, 2001Assignee: Hitachi, Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 6195306Abstract: A semiconductor device has a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits are deactivated.Type: GrantFiled: April 12, 1999Date of Patent: February 27, 2001Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Patent number: 6175251Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: April 15, 1999Date of Patent: January 16, 2001Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
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Patent number: 6160744Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.Type: GrantFiled: July 27, 1999Date of Patent: December 12, 2000Assignees: Hitachi, Ltd., Hitachi VSLI Engineering Corp.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 6154062Abstract: This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks.Type: GrantFiled: August 28, 1998Date of Patent: November 28, 2000Assignee: Hitachi, Ltd.Inventors: Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi
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Patent number: 6107836Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: November 25, 1998Date of Patent: August 22, 2000Assignee: Hitachi, Ltd.Inventors: Takayuki Kawahara, Ryoichi Hori, Masashi Horiguchi, Ryoichi Kurihara, Kiyoo Itoh, Masakazu Aoki, Takeshi Sakata, Kunio Uchiyama
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Patent number: 6107869Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.Type: GrantFiled: June 11, 1998Date of Patent: August 22, 2000Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya