Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: A cage, rollers and solid lubricant are all formed integrally into a complete unitary molding with using difference in thermal expansion in a mold. Assembling the complete unitary molding into the race in the rolling-contact bearing is made easier. The complete unitary molding is made such that the rollers remain exposed partially at their rolling surfaces above the inside circular surface of the complete unitary molding while the solid lubricant on the outside circular surface of the complete unitary molding is squeezed out from between the rolling surfaces of the rollers and the inside circular surface of the outside mold upon molding operation, thereby getting the rolling surfaces of the rollers exposed partially. The mold is composed of an outside mold, an inside mold and an intermediate mold, which is made of a substance larger in thermal expansion than other substance for the outside and inside molds.

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

Abstract: A non-volatile semiconductor memory device provides for higher integration by reducing the area of occupation of direct peripheral circuits, in which the memory cell of an AND type flash memory includes a selection gate, a float gate, a control gate that functions as a word line, and an n-type semiconductor region (source, drain) that functions as a local bit line. A pair of local bit lines adjacent to each other in a memory mat are connected with one global bit line at one end in the direction of the column of the memory mat, and a selection MOS transistor, formed by one enhancement type MOS transistor and one depletion type MOS transistor; is connected in series with each of the pair of local bit lines. One of the local bit lines is selected by turning the selection MOS transistor on/off.

Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Abstract: Respective nodes N1 to N3 only detect a carrier, and the node N3 sets a random time between a time after a certain period of time t1 and a time until a certain period of time t2 after the carrier of data D11 is gone as a waiting time so as to transmit data within this waiting time. The node N2 transmits ACK data D12 with respect to the data D11 to the node N1 before the certain period of time t1 after the carrier of the data D11 is gone. The node N3 detects the carrier of the ACK data D12 and again sets a random time after the certain period of time t1 until the certain period of time t2 to transmit the data.

Abstract: A liquid-ejection head includes a substrate, an inlet formed through the substrate, an outlet for ejecting a liquid, a flow channel leading to the outlet, and a pressure-generating part including a pressure-generating element disposed on a surface of the substrate in the flow channel to generate pressure for ejecting the liquid. The flow channel includes a first flow channel defined above the surface of the substrate on which the pressure-generating element is disposed and a second flow channel defined on the substrate down to below the surface on which the pressure-generating element is disposed. The first and second flow channels extend from an opening of the outlet to the pressure-generating element. The second flow channel has a larger width than the first flow channel.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: Nodes (N1 to N3) include MTU length calculation sections (31 to 33) which multiply baud rates (D21 to D23) of communication parameters (D11 to D13) set based on results of negotiation with other nodes (N1 to N3) by a communication regulated time used in timer control for transmission/reception, and which calculate MTU lengths as maximum packet lengths of the packets based on the multiplication results so that transmission times of the packets for the destination nodes are equal to each other, and also include communication control sections (21 to 23) which divide data to be transmitted to destination nodes into packets having the calculated MTU length to transmit the packets.

Abstract: A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Abstract: According to the present invention, there are provided an ink jet recording head capable of performing high-precision printing and recording and having a high reliability, and a method of manufacturing the head. The ink jet recording head of the present invention has: an element substrate on whose surface an ink discharge energy generating element is formed and which is made of silicon; and a thin and flat inorganic substrate in which an ink discharge port is formed in a portion disposed vertically above the ink discharge energy generating element. Furthermore, the head includes a photosensitive material layer which bonds the element substrate to the inorganic substrate and which is to constitute a wall forming an ink flow path which communicates with the ink discharge port. The inorganic substrate is laminated on the element substrate provided with the photosensitive material layer, and is thereafter provided with the ink discharge port.

Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

Abstract: A display operation mediating means is placed between an application executing means for selectively executing a plurality of applications and generating display control information for each application, and first and second display devices. In this display operation mediating means, priorities are preset for a plurality of pieces of display control information expected to be generated when the plurality of applications are executed. When a plurality of pieces of display control information are generated by the application executing means, the supply of the plurality of pieces of generated display control information to the first and second display devices is mediated in accordance with the stored priorities.