Patents by Inventor Masataka Mizukoshi

Masataka Mizukoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030200654
    Abstract: A method of manufacturing an electronic circuit component, comprises the steps of: (a) forming a first thin film circuit element on a surface of a circuit board made of an Si substrate; (b) forming a hole or trench from the surface of the circuit board through at least a portion of a thickness of the Si substrate by etching; (c) forming an insulating film covering a surface of the formed hole or trench; (d) adhering a dry film of photoresist to the surface of the circuit board, the dry film capping an opening of the hole or trench; (e) patterning the dry film; and (f) by using the patterned dry film as a mask, etching the insulating film. An electronic circuit component having through conductors and being less influenced by high temperature annealing can be manufactured.
    Type: Application
    Filed: April 23, 2003
    Publication date: October 30, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Koji Omote, Masataka Mizukoshi, Osamu Taniguchi
  • Publication number: 20030173678
    Abstract: The semiconductor device comprises: a substrate 10 having a through-hole 18 formed therethrough; an electrode 12 formed on one surface of the substrate 10, through-electrode 38 formed in the through-hole 18 and electrically connected to the electrode 12. The through-electrode 38 includes conducting films 26, 32 formed along the inside wall of the through-hole 18, and pin-shaped projection 36 formed on the conducting film exposed on the other surface of the substrate 10. Whereby the pin-shaped projection absorbs stress generated in mounting the semiconductor device, and stable connection can be realized. The pin-shaped projection can be easily formed by plating. A length of the pin-shaped projection can be freely controlled. Accordingly, the through-electrode having the pin-shaped projection can be stably formed without restrictions of shapes and lengths of the hole formed in a substrate.
    Type: Application
    Filed: February 14, 2003
    Publication date: September 18, 2003
    Applicant: Fujitsu Limited
    Inventor: Masataka Mizukoshi
  • Publication number: 20030148593
    Abstract: An electrode connecting method of connecting a first electrode and a second electrode is disclosed. The respective bonding surfaces of the first and second electrodes are activated. Then, each of the first and second electrodes having the activated surfaces is coated with a coating member for maintaining an activated state. A solid state bond between the first electrode and the second electrode is formed by pressure welding the first electrode and the second electrode so that the first and second electrodes break through the coating members.
    Type: Application
    Filed: January 21, 2003
    Publication date: August 7, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Keishiro Okamoto, Masataka Mizukoshi, Yasuo Yamagishi
  • Publication number: 20030129814
    Abstract: According to the present invention, of the resist film applied to the entire surface of the silicon substrate, the part on the electrode pattern is removed and an opening shaped like a dish in which the diameter of the upper part is larger than that of the lower part is formed, wherein the diameter of the lower part is smaller than the outer diameter of the electrode pattern. The electrode pattern exposed at the bottom of the opening is removed by the etching process. Next, the silicon substrate is tilted and a laser beam is irradiated toward the silicon substrate exposed at the bottom of the opening with water running over the surface of the resist film in air, and a hole is formed.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 10, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Masataka Mizukoshi
  • Publication number: 20030124868
    Abstract: A pattern forming method comprising the steps of: detecting a position of a base pattern formed on a substrate; forming a photosensitive resin film on the substrate; correcting a pattern data of a pattern to be formed on the substrate, based on a positional information of the base pattern to thereby compute a corrected pattern data; displaying a mask pattern on a liquid crystal panel, based on the corrected pattern data; and exposing the photosensitive resin film with the liquid crystal panel as a mask and developing the same to thereby pattern the photosensitive resin film. Even when a base pattern has rotations, shrinkages, distortions, etc., a prescribed upper layer pattern can be formed in alignment with the lower layer pattern.
    Type: Application
    Filed: December 17, 2002
    Publication date: July 3, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Masataka Mizukoshi
  • Patent number: 6580169
    Abstract: The present invention relates to a method for forming bumps on a substrate provided with electrode pads. The method includes providing a mask having openings corresponding to the electrode pads, filling each of the openings with a solder paste, and heat treating the solder paste, wherein the solder paste includes solder powder. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is greater than the thickness of the mask and no more than 1.5 times this thickness. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is not less than 40% the diameter of the opening portions, or no less than 30 wt % of particles whose diameter is 40 to 100% the thickness of the mask.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: June 17, 2003
    Assignee: Fujitsu Limited
    Inventors: Seiki Sakuyama, Yasuo Yamagishi, Masataka Mizukoshi
  • Publication number: 20030090345
    Abstract: A process to manufacture a surface-conductive resin in a short time at a low cost without damaging the main chain of a polymer is provided. The process for manufacturing surface-conductive resin comprises partially substituting a reactive group in at least one of a resin precursor and a semi-cured resin having at least one reactive group partially substitutable under alkaline condition by an alkali metal ion solution, exchanging the substituted alkali metal ion with the ion of a conductive material in the ionic solution, reducing the ion of the conductive material to deposit the conductive layer, then curing the resin, to get surface-conductive polymer/resin.
    Type: Application
    Filed: September 27, 2002
    Publication date: May 15, 2003
    Inventors: Nawalage Florence Cooray, Kanae Nakagawa, Masataka Mizukoshi
  • Publication number: 20030082897
    Abstract: The present invention relates to a method for forming bumps on a substrate provided with electrode pads. The method includes providing a mask having openings corresponding to the electrode pads, filling each of the openings with a solder paste, and heat treating the solder paste, wherein the solder paste includes solder powder. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is greater than the thickness of the mask and no more than 1.5 times this thickness. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is not less than 40% the diameter of the opening portions, or no less than 30 wt % of particles whose diameter is 40 to 100% the thickness of the mask.
    Type: Application
    Filed: July 10, 2002
    Publication date: May 1, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Seiki Sakuyama, Yasuo Yamagishi, Masataka Mizukoshi
  • Patent number: 6535002
    Abstract: An IC to be tested having solder bumps is mounted on an IC socket mounted on a test board. The IC socket is provided with a contact unit including a plurality of straight contact pins each having an lower end connected to the test board and an upper end connected to the solder bumps and also including an elastic member for supporting the plurality of contact pins. A diameter of the plurality of contact pins is configured to be sufficiently small for the plurality of contact pins to pierce the respective solder bumps so that an electrical connection is established by the upper end of each of the plurality of solder bumps piercing an associated one of the solder bumps.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: March 18, 2003
    Assignee: Fujitsu Limited
    Inventors: Makoto Haseyama, Shigeyuki Maruyama, Masataka Mizukoshi, Futoshi Fukaya
  • Patent number: 6528346
    Abstract: First and second ball forming plates are prepared. The cavities of the first plate and the cavities of the second plate 20 are filled with solder paste, respectively. The first plate and the second plate are placed in a facing relationship to each other and heated to form metal balls each of which corresponds to the total metal components of the solder paste in one cavity of the first plate and one cavity in the second plate. The metal balls are formed in the cavities of the lower plate 10. The metal balls are transferred from the cavities of the first plate to a device on which bumps are to be formed.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: March 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Masayuki Ochiai, Hidefumi Ueda, Michio Sono, Ichiro Yamaguchi, Kazuhiko Mitobe, Koki Otake, Junichi Kasai, Nobuo Kamehara, Yasuo Yamagishi, Masataka Mizukoshi
  • Patent number: 6518163
    Abstract: The present invention relates to a bump formation method, comprising the steps of providing a mask, in which a plurality of openings have been formed corresponding to a plurality of electrode pads, to a substrate provided with this plurality of electrode pads, filling the openings with a solder paste, and heat treating the solder paste. The solder paste contains a solder powder. This solder powder is one that contains no more than 10 wt % particles whose diameter is greater than the thickness of the mask and no more than 1.5 times this thickness. Preferably, this solder powder is one that contains no more than 10 wt % particles whose diameter is greater than 40% of the diameter of the openings, or one that contains no more than 30 wt % particles whose diameter is 40 to 100% the thickness of the mask.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: February 11, 2003
    Assignee: Fujitsu Limited
    Inventors: Seiki Sakuyama, Yasuo Yamagishi, Masataka Mizukoshi
  • Publication number: 20020130164
    Abstract: There are provided a chamber having openings which are opened to an outer air and through which a solder-adhered object w is passed and having a heating/melting area and carrying areas arranged adjacent to the heating/melting area, a carrying mechanism for carrying the solder-adhered object w into the heating/melting area, a formic-acid supplying means for supplying a formic acid into the heating/melting area, an exhausting means for exhausting a gas from the heating/melting area and its neighboring area to lower a pressure in the heating/melting area rather than an outer air, heating means for heating directly or indirectly the solder-adhered object w in the heating/melting area, and air-stream suppressing means for disturbing a gas flow between the heating/melting area and the carrying areas.
    Type: Application
    Filed: October 5, 2001
    Publication date: September 19, 2002
    Applicant: Fujitsu Limited
    Inventors: Hirohisa Matsuki, Hiroyuki Matsui, Eiji Yoshida, Takao Ohno, Koki Otake, Akiyo Mizutani, Motoshu Miyajima, Masataka Mizukoshi, Eiji Watanabe
  • Patent number: 6347037
    Abstract: A semiconductor device includes a board and a semiconductor chip which is connected to an upper surface of the board via face-down bonding. The semiconductor device further includes a frame-shape member which is connected to the upper surface of the board with first adhesive, and has an opening to accommodate the semiconductor chip therein, and a plate-shape member which is situated to cover the semiconductor chip and the frame-shape member, and is connected to the semiconductor chip and the frame-shape member with second adhesive, wherein the frame-shape member has such a sufficient sturdiness as to prevent thermal-expansion-induced deformations of the board and the plate-shape member.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: February 12, 2002
    Assignee: Fujitsu Limited
    Inventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi, Masaru Nukiwa, Takao Akai
  • Patent number: 6344407
    Abstract: A semiconductor device manufacturing method comprises the steps of forming solder bumps on an underlying metal film of a semiconductor device, and placing the semiconductor device and the solder layer in a reduced pressure atmosphere containing formic acid to form the solder bumps. Accordingly, the solder bumps can be formed without flux generating voids in the solder layer. Furthermore, the cleaning required after the solder bumps are formed can be omitted.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: February 5, 2002
    Assignee: Fujitsu Limited
    Inventors: Hirohisa Matsuki, Fumihiko Taniguchi, Kunio Kodama, Eiji Watanabe, Masataka Mizukoshi, Hiroyuki Matsui
  • Publication number: 20020001178
    Abstract: A semiconductor device includes a board and a semiconductor chip which is connected to an upper surface of the board via face-down bonding. The semiconductor device further includes a frame-shape member which is connected to the upper surface of the board with first adhesive, and has an opening to accommodate the semiconductor chip therein, and a plate-shape member which is situated to cover the semiconductor chip and the frame-shape member, and is connected to the semiconductor chip and the frame-shape member with second adhesive, wherein the frame-shape member has such a sufficient sturdiness as to prevent thermal-expansion-induced deformations of the board and the plate-shape member.
    Type: Application
    Filed: November 4, 1998
    Publication date: January 3, 2002
    Inventors: MAKOTO IIJIMA, TETSUSHI WAKABAYASHI, TOSHIO HAMANO, MASAHARU MINAMIZAWA, MASASHI TAKENAKA, TATUROU YAMASHITA, MASATAKA MIZUKOSHI, MASARU NUKIWA, TAKAO AKAI
  • Patent number: 6319810
    Abstract: Method for forming solder bumps on a first member such as a semiconductor chip having electrode pads formed thereon. A flat plate having holes is prepared and the holes are filled with solder paste by squeezing. The flat plate is then overlapped with the first member with the flat plate above the first plate. The flat plate and the first member are heated to a temperature higher than the melting point of the solder alloy in the solder paste. Therefore, solder bumps having identical sizes and uniform structures can be obtained.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: November 20, 2001
    Assignee: Fujitsu Limited
    Inventors: Masayuki Ochiai, Yasuo Yamagishi, Ichiro Yamaguchi, Masahiro Yoshikawa, Koki Otake, Masataka Mizukoshi, Yuuji Watanabe
  • Publication number: 20010018263
    Abstract: First and second ball forming plates are prepared. The cavities of the first plate and the cavities of the second plate 20 are filled with solder paste, respectively. The first plate and the second plate are placed in a facing relationship to each other and heated to form metal balls each of which corresponds to the total metal components of the solder paste in one cavity of the first plate and one cavity in the second plate. The metal balls are formed in the cavities of the lower plate 10. The metal balls are transferred from the cavities of the first plate to a device on which bumps are to be formed.
    Type: Application
    Filed: December 28, 2000
    Publication date: August 30, 2001
    Inventors: Masayuki Ochiai, Hidefumi Ueda, Michio Sono, Ichiro Yamaguchi, Kazuhiko Mitobe, Koki Otake, Junichi Kasai, Nobuo Kamehara, Yasuo Yamagishi, Masataka Mizukoshi
  • Publication number: 20010011898
    Abstract: An IC to be tested having solder bumps is mounted on an IC socket mounted on a test board. The IC socket is provided with a contact unit including a plurality of straight contact pins each having an lower end connected to the test board and an upper end connected to the solder bumps and also including an elastic member for supporting the plurality of contact pins. A diameter of the plurality of contact pins is configured to be sufficiently small for the plurality of contact pins to pierce the respective solder bumps so that an electrical connection is established by the upper end of each of the plurality of solder bumps piercing an associated one of the solder bumps.
    Type: Application
    Filed: March 16, 2001
    Publication date: August 9, 2001
    Applicant: Fujitsu Limited
    Inventors: Makoto Haseyama, Shigeyuki Maruyama, Masataka Mizukoshi, Futoshi Fukaya
  • Publication number: 20010008310
    Abstract: The present invention relates to a bump formation method, comprising the steps of providing a mask, in which a plurality of openings have been formed corresponding to a plurality of electrode pads, to a substrate provided with this plurality of electrode pads, filling the openings with a solder paste, and heat treating the solder paste. The solder paste contains a solder powder. This solder powder is one that contains no more than 10 wt % particles whose diameter is greater than the thickness of the mask and no more than 1.5 times this thickness. Preferably, this solder powder is one that contains no more than 10 wt % particles whose diameter is greater than 40% of the diameter of the openings, or one that contains no more than 30 wt % particles whose diameter is 40 to 100% the thickness of the mask.
    Type: Application
    Filed: March 15, 2001
    Publication date: July 19, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Seiki Sakuyama, Yasuo Yamagishi, Masataka Mizukoshi
  • Patent number: 6229320
    Abstract: An IC to be tested having solder bumps is mounted on an IC socket mounted on a test board. The IC socket is provided with a contact unit including a plurality of straight contact pins each having an lower end connected to the test board and an upper end connected to the solder bumps and also including an elastic member for supporting the plurality of contact pins. A diameter of the plurality of contact pins is configured to be sufficiently small for the plurality of contact pins to pierce the respective solder bumps so that an electrical connection is established by the upper end of each of the plurality of solder bumps piercing an associated one of the solder bumps.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: May 8, 2001
    Assignee: Fujitsu Limited
    Inventors: Makoto Haseyama, Shigeyuki Maruyama, Masataka Mizukoshi, Futoshi Fukaya