Patents by Inventor Masatoshi Fukuda

Masatoshi Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210242191
    Abstract: A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, determines whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body, evacuates, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied, determines whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and returns the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Toshihiko OHDA, Tetsuya KUROSAWA, Masatoshi FUKUDA
  • Patent number: 11024619
    Abstract: A semiconductor manufacturing apparatus that sequentially stacks a plurality of semiconductor chips while aligning the plurality of semiconductor chips on a stage. A condition determinator determines whether an apparatus performing a mounting processing stops during a mounting processing of the plurality of semiconductor chips. An evacuation controller evacuates, when it is determined that the apparatus performing the mounting processing stops, a group of semiconductor chips that has been stacked before the determination. A resuming determinator determines whether to resume the mounting processing after it is determined that the predetermined condition is satisfied. A return controller returns the evacuated group of semiconductor chips to a position before the evacuation and continues the mounting processing when it is determined that the mounting processing is resumed.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 1, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Toshihiko Ohda, Tetsuya Kurosawa, Masatoshi Fukuda
  • Patent number: 10943844
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki, Masatoshi Kawato, Masayuki Miura, Masatoshi Fukuda, Soichi Homma
  • Patent number: 10903200
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 26, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Patent number: 10854576
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Masayuki Miura, Naoyuki Komuta, Yuka Akahane, Yukifumi Oyama
  • Publication number: 20200185373
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
  • Patent number: 10600773
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Publication number: 20190393114
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.
    Type: Application
    Filed: February 5, 2019
    Publication date: December 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Satoshi TSUKIYAMA, Hideo AOKI, Masatoshi KAWATO, Masayuki MIURA, Masatoshi FUKUDA, Soichi HOMMA
  • Publication number: 20190296001
    Abstract: A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, determines whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body, evacuates, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied, determines whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and returns the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Toshihiko Ohda, Tetsuya Kurosawa, Masatoshi Fukuda
  • Patent number: 10354977
    Abstract: A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. The first semiconductor-chip is located above the wiring substrate. A second semiconductor-chip has a third face, a fourth face, a second side face between an outer edge of the third face and an outer edge of the fourth face, and a through electrode passing through at least a semiconductor substrate between the third face and the fourth face. The second side face is the first condition plane and a second condition plane having more irregularities than the first condition plane. The second semiconductor-chip is located between the wiring substrate and the first semiconductor-chip. The resin is located around the first and second semiconductor-chips.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi Homma, Masatoshi Fukuda
  • Publication number: 20180277515
    Abstract: A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. The first semiconductor-chip is located above the wiring substrate. A second semiconductor-chip has a third face, a fourth face, a second side face between an outer edge of the third face and an outer edge of the fourth face, and a through electrode passing through at least a semiconductor substrate between the third face and the fourth face. The second side face is the first condition plane and a second condition plane having more irregularities than the first condition plane. The second semiconductor-chip is located between the wiring substrate and the first semiconductor-chip. The resin is located around the first and second semiconductor-chips.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Soichi Homma, Masatoshi Fukuda
  • Publication number: 20180261574
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Application
    Filed: September 3, 2017
    Publication date: September 13, 2018
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Masayuki MIURA, Naoyuki KOMUTA, Yuka AKAHANE, Yukifumi OYAMA
  • Patent number: 9997484
    Abstract: A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first and second semiconductor elements and electrically connects the first and second semiconductor elements. The bonding portion is between the first and second semiconductor elements, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. The resin portion is between the first and second semiconductor elements. The first semiconductor element is between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first and second semiconductor elements.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 12, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeori Maeda, Masatoshi Fukuda, Ryoji Matsushima, Hideo Aoki
  • Publication number: 20180076187
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 15, 2018
    Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
  • Publication number: 20170263582
    Abstract: A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first and second semiconductor elements and electrically connects the first and second semiconductor elements. The bonding portion is between the first and second semiconductor elements, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. The resin portion is between the first and second semiconductor elements. The first semiconductor element is between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first and second semiconductor elements.
    Type: Application
    Filed: August 30, 2016
    Publication date: September 14, 2017
    Inventors: Takeori MAEDA, Masatoshi FUKUDA, Ryoji MATSUSHIMA, Hideo AOKI
  • Patent number: 9721905
    Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju Yamada, Takashi Yamazaki, Masatoshi Fukuda, Yasuhiro Koshio
  • Patent number: 9570414
    Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Tsukiyama, Masatoshi Fukuda, Yukifumi Oyama, Shinya Fukayama
  • Publication number: 20160276290
    Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.
    Type: Application
    Filed: May 31, 2016
    Publication date: September 22, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju YAMADA, Takashi YAMAZAKI, Masatoshi FUKUDA, Yasuhiro KOSHIO
  • Patent number: 9362196
    Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: June 7, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju Yamada, Takashi Yamazaki, Masatoshi Fukuda, Yasuhiro Koshio
  • Publication number: 20160111317
    Abstract: A semiconductor manufacturing apparatus includes: a collet which sucks a semiconductor chip having a main surface on which a bump is formed, and an actuator which transfers the sucked semiconductor chip onto a mounting substrate or another semiconductor chip by driving the collet. A recessed portion for avoiding a contact between the collet and the bump is formed on a suction surface of the collet which sucks the semiconductor chip.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventors: Shinya FUKAYAMA, Yukifumi OYAMA, Satoshi TSUKIYAMA, Masatoshi FUKUDA