Patents by Inventor Masatoshi Fukuda
Masatoshi Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979312Abstract: An end-to-end path can be set without providing a hierarchy in a control device of a multi-domain network. A path setting system (10) includes an orchestrator 200 and a control device (100). The orchestrator (200) generates path candidates corresponding to a line of domains through which paths that are candidates for a path pass and transmits the path candidates to control devices (100) of domains through which the path candidates pass to request setting of the path. The control device (100) acquires, from the control devices (100) of other domains through which path candidates pass, metrics of the path candidates in the domains, calculates total metrics, selects an optimum path, and sets the optimum path.Type: GrantFiled: July 1, 2020Date of Patent: May 7, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Aki Fukuda, Masatoshi Saito, Hirotaka Yoshioka
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Patent number: 11749667Abstract: A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, determines whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body, evacuates, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied, determines whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and returns the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.Type: GrantFiled: April 19, 2021Date of Patent: September 5, 2023Assignee: Kioxia CorporationInventors: Toshihiko Ohda, Tetsuya Kurosawa, Masatoshi Fukuda
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Publication number: 20230262100Abstract: To effectively protect performers in an online interaction event. There is provided an information processing device including a call control unit that controls a video call between a performer terminal used by a performer and a participant terminal used by a participant, in which the call control unit forcibly terminates the video call on the basis of a stop request received from the performer terminal or an observer terminal used by an observer who monitors the video call.Type: ApplicationFiled: June 2, 2021Publication date: August 17, 2023Inventors: MASAKO KADOBAYASHI, MASATOSHI FUKUDA
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Publication number: 20230177787Abstract: A right holder information checking unit (55) (checking unit) of a content checking device (12) (information processing device) checks whether content (45) posted by a poster (40) to a virtual space in which one or more pieces of content can be shared has right holder information indicating that the content is appropriate content permitted to be posted by the right holder of the content (45).Type: ApplicationFiled: April 28, 2021Publication date: June 8, 2023Applicants: SONY GROUP CORPORATION, SONY INTERACTIVE ENTERTAINMENT INC.Inventors: Masashi NAKATA, Takashi IMAMURA, Mihee KANG, Masatoshi FUKUDA, Yoshio KONNO, Junichi TANAKA, Takuma DOMAE
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Publication number: 20210242191Abstract: A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, determines whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body, evacuates, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied, determines whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and returns the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.Type: ApplicationFiled: April 19, 2021Publication date: August 5, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Toshihiko OHDA, Tetsuya KUROSAWA, Masatoshi FUKUDA
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Patent number: 11024619Abstract: A semiconductor manufacturing apparatus that sequentially stacks a plurality of semiconductor chips while aligning the plurality of semiconductor chips on a stage. A condition determinator determines whether an apparatus performing a mounting processing stops during a mounting processing of the plurality of semiconductor chips. An evacuation controller evacuates, when it is determined that the apparatus performing the mounting processing stops, a group of semiconductor chips that has been stacked before the determination. A resuming determinator determines whether to resume the mounting processing after it is determined that the predetermined condition is satisfied. A return controller returns the evacuated group of semiconductor chips to a position before the evacuation and continues the mounting processing when it is determined that the mounting processing is resumed.Type: GrantFiled: September 10, 2018Date of Patent: June 1, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Toshihiko Ohda, Tetsuya Kurosawa, Masatoshi Fukuda
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Patent number: 10943844Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.Type: GrantFiled: February 5, 2019Date of Patent: March 9, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Tsukiyama, Hideo Aoki, Masatoshi Kawato, Masayuki Miura, Masatoshi Fukuda, Soichi Homma
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Patent number: 10903200Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.Type: GrantFiled: February 18, 2020Date of Patent: January 26, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
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Patent number: 10854576Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.Type: GrantFiled: September 3, 2017Date of Patent: December 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Masayuki Miura, Naoyuki Komuta, Yuka Akahane, Yukifumi Oyama
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Publication number: 20200185373Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
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Patent number: 10600773Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.Type: GrantFiled: March 1, 2017Date of Patent: March 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
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Publication number: 20190393114Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.Type: ApplicationFiled: February 5, 2019Publication date: December 26, 2019Applicant: Toshiba Memory CorporationInventors: Satoshi TSUKIYAMA, Hideo AOKI, Masatoshi KAWATO, Masayuki MIURA, Masatoshi FUKUDA, Soichi HOMMA
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Publication number: 20190296001Abstract: A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, determines whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body, evacuates, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied, determines whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and returns the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.Type: ApplicationFiled: September 10, 2018Publication date: September 26, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Toshihiko Ohda, Tetsuya Kurosawa, Masatoshi Fukuda
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Patent number: 10354977Abstract: A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. The first semiconductor-chip is located above the wiring substrate. A second semiconductor-chip has a third face, a fourth face, a second side face between an outer edge of the third face and an outer edge of the fourth face, and a through electrode passing through at least a semiconductor substrate between the third face and the fourth face. The second side face is the first condition plane and a second condition plane having more irregularities than the first condition plane. The second semiconductor-chip is located between the wiring substrate and the first semiconductor-chip. The resin is located around the first and second semiconductor-chips.Type: GrantFiled: September 12, 2017Date of Patent: July 16, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Soichi Homma, Masatoshi Fukuda
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Publication number: 20180277515Abstract: A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. The first semiconductor-chip is located above the wiring substrate. A second semiconductor-chip has a third face, a fourth face, a second side face between an outer edge of the third face and an outer edge of the fourth face, and a through electrode passing through at least a semiconductor substrate between the third face and the fourth face. The second side face is the first condition plane and a second condition plane having more irregularities than the first condition plane. The second semiconductor-chip is located between the wiring substrate and the first semiconductor-chip. The resin is located around the first and second semiconductor-chips.Type: ApplicationFiled: September 12, 2017Publication date: September 27, 2018Applicant: Toshiba Memory CorporationInventors: Soichi Homma, Masatoshi Fukuda
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Publication number: 20180261574Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.Type: ApplicationFiled: September 3, 2017Publication date: September 13, 2018Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Masayuki MIURA, Naoyuki KOMUTA, Yuka AKAHANE, Yukifumi OYAMA
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Patent number: 9997484Abstract: A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first and second semiconductor elements and electrically connects the first and second semiconductor elements. The bonding portion is between the first and second semiconductor elements, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. The resin portion is between the first and second semiconductor elements. The first semiconductor element is between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first and second semiconductor elements.Type: GrantFiled: August 30, 2016Date of Patent: June 12, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takeori Maeda, Masatoshi Fukuda, Ryoji Matsushima, Hideo Aoki
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Publication number: 20180076187Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.Type: ApplicationFiled: March 1, 2017Publication date: March 15, 2018Inventors: Yuji KARAKANE, Masatoshi FUKUDA, Soichi HOMMA, Naoyuki KOMUTA, Yukifumi OYAMA
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Publication number: 20170263582Abstract: A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first and second semiconductor elements and electrically connects the first and second semiconductor elements. The bonding portion is between the first and second semiconductor elements, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. The resin portion is between the first and second semiconductor elements. The first semiconductor element is between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first and second semiconductor elements.Type: ApplicationFiled: August 30, 2016Publication date: September 14, 2017Inventors: Takeori MAEDA, Masatoshi FUKUDA, Ryoji MATSUSHIMA, Hideo AOKI
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Patent number: 9721905Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.Type: GrantFiled: May 31, 2016Date of Patent: August 1, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Keiju Yamada, Takashi Yamazaki, Masatoshi Fukuda, Yasuhiro Koshio