Abstract: An MTJ memory cell has an access transistor which turns on in response to activation of a corresponding word line and a tunneling magneto-resistance element which has an electric resistance changing in accordance with stored data. The access transistor has a source connected to a source line for supplying a ground voltage. To restrict an off leakage current in a non-selected access transistor, each access transistor is configured with a MOS transistor having a threshold voltage that is larger than that of another MOS transistor formed on the same chip.

Abstract: An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.

Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

Abstract: An access transistor ATR in an MTJ memory cell, which is one of transistors connected to a read current path, is constituted with a surface-channel, field-effect transistor. The surface-channel, field-effect transistor has a channel resistance lower than a channel-embedded, field-effect transistor, and can reduce an RC load in the read current path. Accordingly, data can be read with a high speed.

Abstract: An access transistor in an MTJ memory cell, which is one of transistors connected to a read current path, is fabricated with a semiconductor layer formed on an insulating film on a semiconductor substrate SUB, and includes impurity regions, a gate region and a body region. That is, the access transistor is fabricated with an SOI (Silicon On Insulator) structure in order to reduce an off-leak current.

Abstract: A falling sensor is provided, which detects a falling of a magnetic disk drive or an information processing device installed with said magnetic disk drive and which is effective for avoiding physical damages of magnetic heads and magnetic disk media.

Abstract: A memory array is provided with first MTJ memory cells arranged in alternate rows and second MTJ memory cells arranged in other alternate rows and each having a layout inverted in a Y direction with respect to the first MTJ memory cell. In each memory cell column, first and second transistor gate interconnections are arranged in the Y direction. In the first MTJ memory cell, a gate of a transistor provided as an access element is connected to the first transistor gate interconnection. In the second MTJ memory cell, a gate of a transistor provided as an access element is connected to the second transistor gate interconnection.

Abstract: The present invention relates to a conduit repairing material, repairing structure, and repairing method thereof, and particularly provides a repairing method for an existing conduit characterized by comprising using a plurality of reinforcing members capable of being carried in the existing conduit, assembling said reinforcing members into a hollow skeleton-like reinforcing body extending substantially along the inner surface of the existing conduit, attaching a plurality of inner face bars to the inside of the reinforcing body to assemble them into a tubular form along the lengthwise direction of the conduit, and injecting a curable infilling into the gap between the inner face bars and the inner surface of the existing conduit.

Abstract: A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.

Abstract: A tunneling magneto-resistance element forming an MTJ memory cell is connected between a bit line and a strap. In each memory cell column, the strap is shared by the plurality of tunneling magneto-resistance elements in the same row block. The access transistor is connected between strap and ground voltage, and is turned on/off in response to a corresponding word line. Storage data is read from the selected memory cell based on a comparison between results of data reading effected on a memory cell group coupled to the same strap before and after application of a predetermined magnetic field to the selected memory cell.

Abstract: In a memory cell array of an MRAM, a reference memory cell holding a reference value can generate accurate reference current of an intermediate value of data by uniformly supplying reference current to two sense amplifiers using two cells of a cell holding “H” data and a cell holding “L” data. Each bit line is connected to a data-storing memory cell and to the reference memory cell. When the data-storing memory cell connected to a bit line is accessed, the reference memory cell is accessed on the adjacent bit line. Only one row of reference memory cells is provided, reducing the chip area. Therefore, a non-volatile memory device that can reduce the area of a reference cell occupied on a chip while generating accurate reference current for determination can be provided.

Abstract: A falling sensor is provided, which detects a falling of a magnetic disk drive or a information processing device installed with the magnetic disk drive and which is effective for avoiding physical damage of magnetic heads and magnetic disk media. The magnetic disk drive or the information processing device, include an unload mechanism moving or evacuating the magnetic head from a surface of the magnetic disk media, and a falling sensor comprising a conductive flexible beam or member having a compatible function, a conductive weight supported by these beams and a conductive wall arranged to be made in contact or non-contact with the weight. The sensor can detect a falling of the magnetic disk drive or the information processing device, which is typically a notebook personal computer installed with the magnetic disk drive, and evacuate the magnetic head by the unload mechanism. The conductive wall can be formed of a tubular member.

Abstract: A tunneling magneto-resistance element of each MTJ (magnetic tunnel junction) memory cell is connected between a bit line and a strap. Each strap is shared by a plurality of tunneling magneto-resistance elements that are located adjacent to each other in the row direction in the same sub array. Each access transistor is connected between a corresponding strap and a ground voltage, and turned ON/OFF in response to a corresponding word line. Since data read operation can be conducted with the structure that does not have an access transistor for every tunneling magneto-resistance element, the array area can be reduced.

Abstract: An apparatus for manufacturing moldings by which clear colors and patterns can be brought out without a remarkable lowering of strength. Immediately before delivery to a metal mold, outer resin material positioned on the main cylinder inner wall side is put in the molten state, and inner resin material positioned on the main screw side is controlled to be from the softening temperature to the melting temperature both inclusive to be extrusion-molded as they are. The inner wall of the main cylinder is expanded where the outer resin material is received to help the outer resin material be thrown in smoothly.

Abstract: A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external dock signal is generated. The input/output buffer circuit is operated in synchronization with the internal dock signal.

Abstract: An access transistor ATR in an MTJ memory cell, which is one of transistors connected to a read current path, is constituted with a surface-channel, field-effect transistor. The surface-channel, field-effect transistor has a channel resistance lower than a channel-embedded, field-effect transistor, and can reduce an RC load in the read current path. Accordingly, data can be read with a high speed.

Abstract: In a memory cell array of an MRAM, a reference memory cell holding a reference value can generate accurate reference current of an intermediate value of data by uniformly supplying reference current to two sense amplifiers using two cells of a cell holding “H” data and a cell holding “L” data. Each bit line is connected to a data-storing memory cell and to the reference memory cell. When the data-storing memory cell connected to a bit line is accessed, the reference memory cell is accessed on the adjacent bit line. Only one row of reference memory cells is provided, reducing the chip area. Therefore, a non-volatile memory device that can reduce the area of a reference cell occupied on a chip while generating accurate reference current for determination can be provided.

Abstract: An access transistor in an MTJ memory cell, which is one of transistors connected to a read current path, is fabricated with a semiconductor layer formed on an insulating film on a semiconductor substrate SUB, and includes impurity regions, a gate region and a body region. That is, the access transistor is fabricated with an SOI (Silicon On Insulator) structure in order to reduce an off-leak current.

Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

Abstract: An MTJ memory cell has an access transistor which turns on in response to activation of a corresponding word line and a tunneling magneto-resistance element which has an electric resistance changing in accordance with stored data. The access transistor has a source connected to a source line for supplying a ground voltage. To restrict an off leakage current in a non-selected access transistor, each access transistor is configured with a MOS transistor having a threshold voltage that is larger than that of another MOS transistor formed on the same chip.