Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

Abstract: Disclosed is a low-power data transfer circuit having a high data transfer rate. This data transfer circuit of the invention includes a first selection circuit for selecting two signal lines out of three signal lines and precharging the remaining signal line to a first potential; and a second selection circuit for selecting and connecting the two data signal lines selected by the first selection circuit to a reception side circuit. With the configuration, a period of precharging a signal line is included in a data transfer period. Thus, there is no need to provide a specific precharge period after data transfer, and data can be transferred effectively.

Abstract: First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.

Abstract: A data transfer circuit including four data lines is provided. In the data transfer circuit, a first driver pulls one of two data lines equalized to an “H” level by a first equalizer to an “L” level for transmitting first data. A second driver pulls one of two data lines equalized to an “L” level by a second equalizer to an “H” level for transmitting second data. A selector connects the two data line pulled to an “H” level to the first driver and the first equalizer and the two data lines pulled to an “L” level to the second driver and the second equalizer. Therefore, equalizing operation can be performed at a high speed and with reduced power consumption.

Abstract: In a DRAM, a data transfer circuit includes a control circuit which selects a data transfer line to be discharged from high to low and a data transfer line to be precharged from low to high for the subsequent data transfer period and turn on an n channel MOS transistor between the selected two data transfer lines for a predetermined period. A positive charge of a data transfer line can be effectively used to reduce current consumption.

Abstract: For a write operation, a synchronous semiconductor memory device in a single-data-rate SDRAM operation mode selects a memory cell column in accordance with a column select signal produced from a write clock produced in synchronization with an external clock signal without shifting the write clock. In a double-data-rate SDRAM operation mode, the synchronous semiconductor memory device selects the memory cell column in accordance with the column select signal produced from the write clock produced in synchronization with the external clock signal and shifted by selected clocks.

Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

Abstract: A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [1], a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.

Abstract: A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external clock signal is generated. The input/output buffer circuit is operated in synchronization with the internal clock signal.

Abstract: Provided is a power supply-to-power supply capacitance cell including a first capacitor connected between a sub power supply line and a sub ground line, a second capacitor connected between a main power supply line and the sub ground line, and a third capacitor connected between the sub power supply line and a main ground line. Thus, a voltage drop of the sub power supply line can be reduced in current consumption of an internal circuit, so that an operation of the internal circuit is stabilized and the operating speed thereof is improved.

Abstract: The semiconductor memory device includes a logic circuit and a memory macro. The memory macro has a region in which memory blocks are formed. Memory spaces are increased in a predetermined order. Address connection lines connecting between the logic circuit and the memory macro alter a connecting relation such that consecutive addresses are realized in each bank. A word line address specified by the logic circuit is used in the memory macro with no change therein.

Abstract: Shift switches are divided into a plurality of shift switch groups each having the same number of shift switches. The connection direction of each shift switch is switched at the shift switch corresponding to the shift position. The designation of the shift position is carried out by decoding an upper predecoding signal for designating what shift switch group the shift switch corresponding to the shift position belongs to and a lower predecoding signal for designating where the shift switch corresponding to the shift position is located in the shift switches belonging to the same shift switch group. Since the lower predecoding signal can be used as a common signal for each shift switch group, the scale of the decoding circuit for decoding the designation of the shift position can be restrained.

Abstract: A read gate of a DRAM core cell includes first and second N channel MOS transistors having gates connected to a pair of bit lines through first and second nodes, respectively, and third and fourth MOS transistors having gates both of which receive a column selecting signal, with gate oxide films of the third and the fourth N channel MOS transistors being formed to be thinner than gate oxide films of the first and the second N channel MOS transistors. It is accordingly possible to lower an amplitude voltage of the column selecting signal, thereby enabling reduction of electric current consumption and speed-up of an operating rate of the DRAM core cell.

Abstract: A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external clock signal is generated. The input/output buffer circuit is operated in synchronization with the internal clock signal.

Abstract: Provided is a power supply-to-power supply capacitance cell including a first capacitor connected between a sub power supply line and a sub ground line, a second capacitor connected between a main power supply line and the sub ground line, and a third capacitor connected between the sub power supply line and a main ground line. Thus, a voltage drop of the sub power supply line can be reduced in current consumption of an internal circuit, so that an operation of the internal circuit is stabilized and the operating speed thereof is improved.

Abstract: A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.

Abstract: The semiconductor memory device includes a logic circuit and a memory macro. The memory macro has a region in which memory blocks are formed. Memory spaces are increased in a predetermined order. Address connection lines connecting between the logic circuit and the memory macro alter a connecting relation such that consecutive addresses are realized in each bank. A word line address specified by the logic circuit is used in the memory macro with no change therein.

Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

Abstract: Rapid data transfer and reduction in power consumption can be achieved by reducing the number of row accesses.

Abstract: Rapid data transfer and reduction in power consumption can be achieved by reducing the number of row accesses. A pattern of the memory regions to be selected in memory array is changed by word line mode designation of word line mode control circuit. Memory cells in the same row are selected in a line mode, whereas memory cells in different rows are simultaneously selected in a box mode.