Abstract: A tunneling magneto-resistance element forming an MTJ memory cell is connected between a bit line and a strap. In each memory cell column, the strap is shared by the plurality of tunneling magneto-resistance elements in the same row block. The access transistor is connected between strap and ground voltage, and is turned on/off in response to a corresponding word line. Storage data is read from the selected memory cell based on a comparison between results of data reading effected on a memory cell group coupled to the same strap before and after application of a predetermined magnetic field to the selected memory cell.

Abstract: A memory array is provided with first MTJ memory cells arranged in alternate rows and second MTJ memory cells arranged in other alternate rows and each having a layout inverted in a Y direction with respect to the first MTJ memory cell. In each memory cell column, first and second transistor gate interconnections are arranged in the Y direction. In the first MTJ memory cell, a gate of a transistor provided as an access element is connected to the first transistor gate interconnection. In the second MTJ memory cell, a gate of a transistor provided as an access element is connected to the second transistor gate interconnection.

Abstract: For a write operation, a synchronous semiconductor memory device in a single-data-rate SDRAM operation mode selects a memory cell column in accordance with a column select signal produced from a write clock produced in synchronization with an external clock signal without shifting the write clock. In a double-data-rate SDRAM operation mode, the synchronous semiconductor memory device selects the memory cell column in accordance with the column select signal produced from the write clock produced in synchronization with the external clock signal and shifted by selected clocks.

Abstract: A high-speed vision sensor has: an analog-to-digital converter array 13 including analog-to-digital converters 210 corresponding to respective lines of photodetectors 120 of a photodetector array 11, and a parallel processing system 14 including processing elements 400 and shift registers 410. The processing elements 400 are provided in one to one correspondence with the photodetectors 120. The shift registers 410 are provided in one to one correspondence with the photodetectors 120. Because the processing elements 400 carry out the image processing between neighboring pixels by parallel processing at high speed, independently from the operation in the shift registers 410, the processing and shifting can be performed efficiently.

Abstract: For a write operation, a synchronous semiconductor memory device in a single-data-rate SDRAM operation mode selects a memory cell column in accordance with a column select signal produced from a write clock produced in synchronization with an external clock signal without shifting the write clock. In a double-data-rate SDRAM operation mode, the synchronous semiconductor memory device selects the memory cell column in accordance with the column select signal produced from the write clock produced in synchronization with the external clock signal and shifted by selected clocks.

Abstract: A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

Abstract: A read gate of a DRAM core cell includes first and second N channel MOS transistors having gates connected to a pair of bit lines through first and second nodes, respectively, and third and fourth MOS transistors having gates both of which receive a column selecting signal, with gate oxide films of the third and the fourth N channel MOS transistors being formed to be thinner than gate oxide films of the first and the second N channel MOS transistors. It is accordingly possible to lower an amplitude voltage of the column selecting signal, thereby enabling reduction of electric current consumption and speed-up of an operating rate of the DRAM core cell.

Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

Abstract: The present invention relates to a conduit repairing material, repairing structure, and repairing method thereof, and particularly provides a repairing method for an existing conduit characterized by comprising using a plurality of reinforcing members capable of being carried in the existing conduit, assembling said reinforcing members into a hollow skeleton-like reinforcing body extending substantially along the inner surface of the existing conduit, attaching a plurality of inner face bars to the inside of the reinforcing body to assemble them into a tubular form along the lengthwise direction of the conduit, and injecting a curable infilling into the gap between the inner face bars and the inner surface of the existing conduit.

Abstract: In write operation and read operation, a plurality of bit lines are divided into first and second bit line groups based on a selected memory cell column in a memory array. The first bit line group is connected to one of first and second voltages and the second bit line group is connected to the other voltage. Accordingly, when a word line corresponding to a selected memory cell is activated, the sources and drains of the non-selected memory cells in the selected memory cell row are set to the same voltage level. Therefore, a charging/discharging current resulting from charging and discharging of each bit line is not generated in response to activation of the word line. This prevents erroneous writing to the non-selected memory cells and delay in read operation caused by generation of the charging/discharging current.

Abstract: A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external dock signal is generated. The input/output buffer circuit is operated in synchronization with the internal dock signal.

Abstract: A tunneling magneto-resistance element of each MTJ (magnetic tunnel junction) memory cell is connected between a bit line and a strap. Each strap is shared by a plurality of tunneling magneto-resistance elements that are located adjacent to each other in the row direction in the same sub array. Each access transistor is connected between a corresponding strap and a ground voltage, and turned ON/OFF in response to a corresponding word line. Since data read operation can be conducted with the structure that does not have an access transistor for every tunneling magneto-resistance element, the array area can be reduced.

Abstract: A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.

Abstract: A method of manufacturing a ceramic capacitor relates to a ceramic capacitor having metal plate terminals that absorb thermal stress and mechanical stress caused by flexure of the substrate. A ceramic capacitor element is provided with terminal electrodes at the two side end surfaces facing opposite each other. The metal plate terminals are each connected to one of the terminal electrodes at one end thereof, are each provided with a folded portion in a middle area and a terminal portion to be connected to the outside toward the other end from the folded portion.

Abstract: A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external clock signal is generated. The input/output buffer circuit is operated in synchronization with the internal clock signal.

Abstract: A holder integrated type base board made of synthetic resin integrally molded with a plurality of holders for inserting LEDs on a front face side of a base board main body and a mold therefore. The mold includes a first mold for molding a back face side of the base board main body and a second mold opposed to the first mold for molding the front face side of the base body main body. In addition, the mold includes a holder molding cavity provided at the second mold which is constituted by an insert die capable of being inserted into and detached from the second mold main body. When it is necessary to correct a position of a portion of the holder in a trially fabricated base board, a position of an LED inserting hole in the base board can simply be corrected by drawing the insert die for molding the holder from the mold main body and interchanging the insert die with a new insert die. As such, an entire first mold does not have to be reproduced.

Abstract: An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.

Abstract: Disclosed is a low-power data transfer circuit having a high data transfer rate. This data transfer circuit of the invention includes a first selection circuit for selecting two signal lines out of three signal lines and precharging the remaining signal line to a first potential; and a second selection circuit for selecting and connecting the two data signal lines selected by the first selection circuit to a reception side circuit. With the configuration, a period of precharging a signal line is included in a data transfer period. Thus, there is no need to provide a specific precharge period after data transfer, and data can be transferred effectively.

Abstract: A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.

Abstract: A plurality of memory devices are connected parallel to each other commonly to signal lines extending in one direction, and signals are transmitted in one direction along the signal lines. The sum of the time of signal propagation from a transmission unit to a selected memory device and the time of signal propagation from the selected memory devices to a reception unit is constant for every memory device. Therefore, offset in access times to the memory chips in the memory system can be eliminated.