Patents by Inventor Masaya Nagata

Masaya Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250030528
    Abstract: A terminal includes: a communication unit configured to perform a bidirectional communication including downlink and uplink with a base station by using a frequency division duplex; and a control unit configured to control a communication to be performed by using a time division duplex in a case where there are a terminal that supports the frequency division duplex and a terminal that does not support the frequency division duplex in a same communication area.
    Type: Application
    Filed: November 19, 2021
    Publication date: January 23, 2025
    Applicant: NTT DOCOMO, INC.
    Inventors: Yuki Takahashi, Shinya Kumagai, Shohei Yoshioka, Masaya Okamura, Mayuko Okano, Satoshi Nagata
  • Publication number: 20250007236
    Abstract: To prevent peeling of a bonding portion between a first substrate having a light emitting element and a second substrate such as an LDD substrate. A light emitting device includes: a first substrate having a light emitting element; and a second substrate bonded to a surface side opposite to a light emitting surface of the light emitting element, in which the first substrate includes: a first conductive layer laminated on the opposite surface side of the light emitting element; a second conductive layer that is laminated on the first conductive layer and reflects light emitted from the light emitting element to the opposite surface side; a third conductive layer laminated on the second conductive layer and bonded to the second substrate via a bonding member; and an insulating layer laminated on the third conductive layer so as to cover at least end portions of the second conductive layer and the third conductive layer laminated.
    Type: Application
    Filed: October 17, 2022
    Publication date: January 2, 2025
    Inventors: MASAYA NAGATA, HIROSHI ISOBE
  • Patent number: 11784197
    Abstract: The present technology relates to a solid-state imaging unit that makes it possible to increase the number of terminals, a method of producing the same, and an electronic apparatus. A solid-state imaging unit includes: an image sensor substrate including a light receiving region in which pixels that each convert incoming light to an electric signal are arranged in a matrix; a solder ball; a glass substrate opposite the image sensor substrate and the solder ball; and a through electrode that couples a wiring line pattern and the solder ball to each other by penetrating a glass adhesive resin interposed between the wiring line pattern and the solder ball. The solder ball is disposed outside the image sensor substrate in a plane direction. The wiring line pattern being formed on the glass substrate. The present disclosure is applicable, for example, to a package and the like including the image sensor substrate.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: October 10, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masaya Nagata, Satoru Wakiyama
  • Publication number: 20230283042
    Abstract: Problems when a first pad on a first substrate for outputting a drive signal for driving a light-emitting element is bonded to a second pad on a second substrate having the light-emitting element are prevented. A light-emitting device includes a first substrate that outputs a drive signal for a light-emitting element, and a second substrate that is laminated on the first substrate and includes the light-emitting element. A first surface side of the first substrate includes a first pad that supplies the drive signal to the light-emitting element, a first conductive layer disposed on the first pad, and a bonding layer disposed on the first conductive layer, and a second surface side of the second substrate facing the first surface of the first substrate includes the light-emitting element having a mesa shape, and a second pad that is disposed on the light-emitting element and bonded to the first pad.
    Type: Application
    Filed: July 14, 2021
    Publication date: September 7, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masaya NAGATA
  • Patent number: 11594563
    Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: February 28, 2023
    Assignee: SONY CORPORATION
    Inventors: Atsushi Yamamoto, Shinji Miyazawa, Yutaka Ooka, Kensaku Maeda, Yusuke Moriya, Naoki Ogawa, Nobutoshi Fujii, Shunsuke Furuse, Masaya Nagata, Yuichi Yamamoto
  • Publication number: 20220415953
    Abstract: An imaging device to which a simple mounting method can be applied is configured. The imaging device is provided with an imaging element, a wiring substrate, and a sealing portion. The imaging element is provided with an image pickup chip over which an light transmitting portion transmitting incident light is arranged and which generates an image signal on the basis of the incident light that has passed through the light transmitting portion, and a pad which is arranged on a bottom surface of the image pickup chip different from a surface on which the light transmitting portion is arranged, which the pad transmitting the generated image signal. The wiring substrate has wiring connected to the pad and extending to a region outside the imaging element, and has the imaging element arranged on a surface thereof. The sealing portion is arranged adjacent to a side surface which is a surface adjacent to the bottom surface of the imaging element, and seals the imaging element.
    Type: Application
    Filed: September 30, 2020
    Publication date: December 29, 2022
    Inventor: MASAYA NAGATA
  • Publication number: 20220310680
    Abstract: The present disclosure relates to a backside illumination type solid-state imaging device, a manufacturing method for a backside illumination type solid-state imaging device, an imaging apparatus, and electronic equipment by which the manufacturing cost can be reduced. A singulated memory circuit and a singulated logic circuit are laid out in a horizontal direction and are embedded by an oxide film and flattened, and then are stacked so as to be contained in a plane direction under a solid-state imaging element. The present disclosure can be applied to an imaging apparatus.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Taizo TAKACHI, Yuichi YAMAMOTO, Suguru SAITO, Satoru WAKIYAMA, Yoichi OOTSUKA, Naoki KOMAI, Kaori TAKIMOTO, Tadashi IIJIMA, Masaki HANEDA, Masaya NAGATA
  • Publication number: 20220246655
    Abstract: The present technology relates to a solid-state imaging unit that makes it possible to increase the number of terminals, a method of producing the same, and an electronic apparatus. A solid-state imaging unit includes: an image sensor substrate including a light receiving region in which pixels that each convert incoming light to an electric signal are arranged in a matrix; a solder ball; a glass substrate opposite the image sensor substrate and the solder ball; and a through electrode that couples a wiring line pattern and the solder ball to each other by penetrating a glass adhesive resin interposed between the wiring line pattern and the solder ball. The solder ball is disposed outside the image sensor substrate in a plane direction. The wiring line pattern being formed on the glass substrate. The present disclosure is applicable, for example, to a package and the like including the image sensor substrate.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masaya NAGATA, Satoru WAKIYAMA
  • Publication number: 20220157873
    Abstract: A semiconductor device includes a first semiconductor substrate in which a pixel region where pixel portions performing photoelectric conversion are two-dimensionally arranged is formed and a second semiconductor substrate in which a logic circuit processing a pixel signal output from the pixel portion is formed, the first and second semiconductor substrates being laminated. A protective substrate protecting an on-chip lens is disposed on the on-chip lens in the pixel region of the first semiconductor substrate with a sealing resin interposed therebetween.
    Type: Application
    Filed: February 2, 2022
    Publication date: May 19, 2022
    Applicant: SONY GROUP CORPORATION
    Inventors: Naoki KOMAI, Naoto SASAKI, Naoki OGAWA, Takashi OINOUE, Hayato IWAMOTO, Yutaka OOKA, Masaya NAGATA
  • Patent number: 11335715
    Abstract: The present technology relates to a solid-state imaging unit that makes it possible to increase the number of terminals, a method of producing the same, and an electronic apparatus. A solid-state imaging unit includes: an image sensor substrate including a light receiving region in which pixels that convert incoming light to an electric signal are arranged in a matrix; a solder ball; a glass substrate opposite the image sensor substrate and the solder ball; and a through electrode that couples a wiring line pattern and the solder ball to each other by penetrating a glass adhesive resin interposed between the wiring line pattern and the solder ball. The solder ball is disposed outside the image sensor substrate in a plane direction. The wiring line pattern being formed on the glass substrate. The present disclosure is applicable, for example, to a package and the like including the image sensor substrate.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: May 17, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masaya Nagata, Satoru Wakiyama
  • Patent number: 11282911
    Abstract: Display devices, display modules, and methods of manufacture are disclosed. In one example, a display device includes a pixel region in which pixels for displaying an image are arranged, on an upper surface of a substrate. A device-side signal electrode for exchanging a signal related to the pixels with an outside is disposed on a side surface of the substrate. A module casing is configured to store the display device and to have a casing-side signal electrode electrically connected to the device-side signal electrode in a spot facing the device-side signal electrode.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: March 22, 2022
    Assignee: Sony Group Corporation
    Inventors: Hiroshi Horikoshi, Masato Kawashima, Kaori Takimoto, Masaya Nagata
  • Publication number: 20210305300
    Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.
    Type: Application
    Filed: January 8, 2021
    Publication date: September 30, 2021
    Applicant: SONY CORPORATION
    Inventors: Atsushi YAMAMOTO, Shinji MIYAZAWA, Yutaka OOKA, Kensaku MAEDA, Yusuke MORIYA, Naoki OGAWA, Nobutoshi FUJII, Shunsuke FURUSE, Masaya NAGATA, Yuichi YAMAMOTO
  • Patent number: 11024658
    Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 1, 2021
    Assignee: SONY CORPORATION
    Inventors: Atsushi Yamamoto, Shinji Miyazawa, Yutaka Ooka, Kensaku Maeda, Yusuke Moriya, Naoki Ogawa, Nobutoshi Fujii, Shunsuke Furuse, Masaya Nagata, Yuichi Yamamoto
  • Patent number: 10804312
    Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit 5 of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive 10 material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: October 13, 2020
    Assignee: Sony Corporation
    Inventors: Masaya Nagata, Kaori Takimoto
  • Publication number: 20200273897
    Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.
    Type: Application
    Filed: March 2, 2020
    Publication date: August 27, 2020
    Applicant: SONY CORPORATION
    Inventors: Atsushi YAMAMOTO, Shinji MIYAZAWA, Yutaka OOKA, Kensaku MAEDA, Yusuke MORIYA, Naoki OGAWA, Nobutoshi FUJII, Shunsuke FURUSE, Masaya NAGATA, Yuichi YAMAMOTO
  • Publication number: 20200258924
    Abstract: The present disclosure relates to a backside illumination type solid-state imaging device, a manufacturing method for a backside illumination type solid-state imaging device, an imaging apparatus, and electronic equipment by which the manufacturing cost can be reduced. A singulated memory circuit and a singulated logic circuit are laid out in a horizontal direction and are embedded by an oxide film and flattened, and then are stacked so as to be contained in a plane direction under a solid-state imaging element. The present disclosure can be applied to an imaging apparatus.
    Type: Application
    Filed: October 16, 2018
    Publication date: August 13, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Taizo TAKACHI, Yuichi YAMAMOTO, Suguru SAITO, Satoru WAKIYAMA, Yoichi OOTSUKA, Naoki KOMAI, Kaori TAKIMOTO, Tadashi IIJIMA, Masaki HANEDA, Masaya NAGATA
  • Publication number: 20200203408
    Abstract: The present technology relates to a solid-state imaging unit that makes it possible to increase the number of terminals, a method of producing the same, and an electronic apparatus. A solid-state imaging unit includes: an image sensor substrate including a light receiving region in which pixels that convert incoming light to an electric signal are arranged in a matrix; a solder ball; a glass substrate opposite the image sensor substrate and the solder ball; and a through electrode that couples a wiring line pattern and the solder ball to each other by penetrating a glass adhesive resin interposed between the wiring line pattern and the solder ball. The solder ball is disposed outside the image sensor substrate in a plane direction. The wiring line pattern being formed on the glass substrate. The present disclosure is applicable, for example, to a package and the like including the image sensor substrate.
    Type: Application
    Filed: August 8, 2018
    Publication date: June 25, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masaya NAGATA, Satoru WAKIYAMA
  • Patent number: 10608028
    Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 31, 2020
    Assignee: SONY CORPORATION
    Inventors: Atsushi Yamamoto, Shinji Miyazawa, Yutaka Ooka, Kensaku Maeda, Yusuke Moriya, Naoki Ogawa, Nobutoshi Fujii, Shunsuke Furuse, Masaya Nagata, Yuichi Yamamoto
  • Publication number: 20190341417
    Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
    Type: Application
    Filed: July 19, 2019
    Publication date: November 7, 2019
    Applicant: Sony Corporation
    Inventors: Masaya NAGATA, Kaori TAKIMOTO
  • Patent number: RE48590
    Abstract: A semiconductor device is provided, including a semiconductor substrate that includes a semiconductor; an electrode layer formed above a first surface side inside the semiconductor substrate; a conductor layer formed above the electrode layer and above the first surface of the semiconductor substrate; a hole formed through the semiconductor substrate from a second surface of the semiconductor substrate to the conductor layer; and a wiring layer that is electrically connected to the electrode layer via the conductor layer at an end portion of the vertical hole, and that extends to the second surface of the semiconductor substrate, the wiring layer being physically separated from the electrode layer by an insulating layer disposed therebetween.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 8, 2021
    Assignee: SONY CORPORATION
    Inventor: Masaya Nagata