Patents by Inventor Masayoshi Kinoshita
Masayoshi Kinoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040082757Abstract: This invention relates to new polypeptide compound represented by the following formula (I), wherein R1, R2, R3, R4, R5, R6, and R7 are described in the specification, or a salt thereof which have antimicrobial activities (especially, antifungal activities), inhibitory activity on &bgr;-1,3-glucan synthase, to process for preparation thereof, to a pharmaceutical composition comprising the same, and to a method for the prophylactic and/or therapeutic treatment of infectious diseases including Pneumocystis carinii infection (e.g. Pneumocystis carinii pneumonia) in a human being or an animal.Type: ApplicationFiled: August 25, 2003Publication date: April 29, 2004Inventors: Katsuhiko Ito, Yutaka Nishihara, Mitsutaka Matsurura, Kazumi Kawai, Masayoshi Kinoshita, Tomoji Higaki, Shigehiro Takase, Hidenori Ohki
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Patent number: 6686782Abstract: A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground.Type: GrantFiled: January 24, 2002Date of Patent: February 3, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masayoshi Kinoshita, Jun Kajiwara, Shiro Sakiyama
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Patent number: 6684378Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.Type: GrantFiled: November 5, 2001Date of Patent: January 27, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Yamamoto, Shirou Sakiyama, Hiroyuki Nakahira, Masayoshi Kinoshita, Katsuji Satomi, Jun Kajiwara, Shinichi Yamamoto
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Patent number: 6646342Abstract: A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit. As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics.Type: GrantFiled: March 14, 2002Date of Patent: November 11, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shiro Sakiyama, Jun Kajiwara, Masayoshi Kinoshita
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Publication number: 20030085461Abstract: A multi-chip module is implemented by connecting a plurality of connection pads provided on, for example, two semiconductor chips via a plurality of conductive connecting members. To carry out a test for determining the quality of the connection between the two semiconductor chips, the multi-chip module is further provided with a plurality of switch elements so that the plurality of connecting members can be electrically conducted in a serial manner via the connection pads of the semiconductor chips. During the connection test, all the switch elements are turned on, and the impedance between both ends of the line including the plurality of connecting members conducted in a serial manner is measured using two probing pads.Type: ApplicationFiled: October 2, 2002Publication date: May 8, 2003Inventors: Shiro Sakiyama, Masayoshi Kinoshita, Jun Kajiwara
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Patent number: 6531856Abstract: During an intermittent operation mode, a switch is normally opened and a capacitor with a large capacitance is isolated from a circuit. Under this condition, a power source voltage is intermittently supplied to a driven device. Since a charge/discharge current of the capacitor during the intermittent operation mode is limited to the charge/discharge current of the capacitor with a small capacitance, the power consumption can be lowered. In addition, since no switch exists in the current path from a power source voltage conversion circuit to the driven device, there is no drop, due to a switch, in the voltage supplied from the power source voltage conversion circuit to the driven device. On the other hand, during a continuous operation mode in which power source voltage is continuously provided to the driven device, the switch is normally closed and a capacitor with a large capacitance is connected to the power source system. Then the noise level in the supplied power is lowered.Type: GrantFiled: August 3, 2001Date of Patent: March 11, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shiro Sakiyama, Jun Kajiwara, Masayoshi Kinoshita
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Publication number: 20030011247Abstract: A power supply device is provided in which, in order to increase a rise speed of an output voltage and to suppress a voltage drop when switching between power supply devices, during a second operation mode in which power supply is stopped, an output switch is turned off and a reference voltage generating circuit applies a reference voltage Vref2, which equals a gate voltage in a steady state during power supply (first operation mode), to the gate of an output transistor. Thus, when entering the first operation mode, the feedback operation of a differential operational amplifier quickly reaches a steady state. In addition, during the second operation mode, a switch that supplies power to the reference voltage generating circuit and the differential operational amplifier is open, reducing the power consumption of the power supply device itself.Type: ApplicationFiled: July 16, 2002Publication date: January 16, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Jun Kajiwara, Masayoshi Kinoshita, Shiro Sakiyama
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Publication number: 20030008424Abstract: A large chip includes a first set of branch wires that branch off from a first trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the first set includes a connection control element and a resistor. A small chip includes a second set of branch wires that branch off from a second trunk wire and extend to respective wires so as to be connected to respective bond pads. Each of the branch wires of the second set includes a connection control element and a resistor. Whether connection is properly made or not between the bond pads is determined by measuring a current value when voltage is applied to first and second test pads.Type: ApplicationFiled: July 8, 2002Publication date: January 9, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Jun Kajiwara, Masayoshi Kinoshita, Shiro Sakiyama
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Patent number: 6490715Abstract: A cell library database includes function information of standard cells which are basic circuits forming a logical device, each of the standard cell comprising at least one of power supply terminal as logical terminals, the function information of the standard cell containing logical information or delay information of the power supply terminal relative to an output terminal, or function information of macro cells which are functional circuits forming a logical device, each of the macro cell comprising at least one of power supply terminals as logical terminals, the function information of the macro cell containing logical information or delay information of said power supply terminals relative to an output terminal. A design aiding system uses the cell library database to execute logical simulation, etc.Type: GrantFiled: April 14, 2000Date of Patent: December 3, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiyuki Moriwaki, Shiro Sakiyama, Hiroo Yamamoto, Jun Kajiwara, Masayoshi Kinoshita
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Publication number: 20020149034Abstract: A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit. As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics.Type: ApplicationFiled: March 14, 2002Publication date: October 17, 2002Inventors: Shiro Sakiyama, Jun Kajiwara, Masayoshi Kinoshita
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Patent number: 6462427Abstract: Each bare-chip IP includes pad electrodes that are of the same size and shape, made of the same material, and arranged in an array at the same pitch over almost the entire surface thereof. A silicon wiring substrate includes pad electrodes that are arranged in an array over almost the entire surface thereof at the same pitch as that between the pad electrodes of the bare-chip IPs. The bare-chip IPs are mounted on the silicon wiring substrate, thereby making a multichip module.Type: GrantFiled: December 21, 2001Date of Patent: October 8, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shiro Sakiyama, Jun Kajiwara, Masayoshi Kinoshita
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Patent number: 6460168Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.Type: GrantFiled: March 27, 2000Date of Patent: October 1, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Yamamoto, Shirou Sakiyama, Hiroyuki Nakahira, Masayoshi Kinoshita, Katsuji Satomi, Jun Kajiwara, Shinichi Yamamoto
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Patent number: 6429633Abstract: In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated nadescending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102.Type: GrantFiled: April 28, 2000Date of Patent: August 6, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Jun Kajiwara, Katsuji Satomi, Shiro Sakiyama, Masayoshi Kinoshita, Katsuhiro Ootani
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Publication number: 20020101263Abstract: A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground.Type: ApplicationFiled: January 24, 2002Publication date: August 1, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masayoshi Kinoshita, Jun Kajiwara, Shiro Sakiyama
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Publication number: 20020079591Abstract: Each bare-chip IP includes pad electrodes that are of the same size and shape, made of the same material, and arranged in an array at the same pitch over almost the entire surface thereof. A silicon wiring substrate includes pad electrodes that are arranged in an array over almost the entire surface thereof at the same pitch as that between the pad electrodes of the bare-chip IPs. The bare-chip IPs are mounted on the silicon wiring substrate, thereby making a multichip module.Type: ApplicationFiled: December 21, 2001Publication date: June 27, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Shiro Sakiyama, Jun Kajiwara, Masayoshi Kinoshita
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Publication number: 20020053897Abstract: In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors 21 through 23 having different on-resistances, which are operated in a descending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor 102.Type: ApplicationFiled: April 28, 2000Publication date: May 9, 2002Inventors: JUN KAJIWARA, KATSUJI SATOMI, SHIRO SAKIYAMA, MASAYOSHI KINOSHITA, KATSUHIRO OOTANI
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Publication number: 20020042902Abstract: A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.Type: ApplicationFiled: November 5, 2001Publication date: April 11, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Yamamoto, Shirou Sakiyama, Hiroyuki Nakahira, Masayoshi Kinoshita, Katsuji Satomi, Jun Kajiwara, Shinichi Yamamoto
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Publication number: 20020030474Abstract: During an intermittent operation mode, a switch is normally opened and a capacitor with a large capacitance is isolated from a circuit. Under this condition, a power source voltage is intermittently supplied to a driven device. Since a charge/discharge current of the capacitor during the intermittent operation mode is limited to the charge/discharge current of the capacitor with a small capacitance, the power consumption can be lowered. In addition, since no switch exists in the current path from a power source voltage conversion circuit to the driven device, there is no drop, due to a switch, in the voltage supplied from the power source voltage conversion circuit to the driven device. On the other hand, during a continuous operation mode in which power source voltage is continuously provided to the driven device, the switch is normally closed and a capacitor with a large capacitance is connected to the power source system. Then the noise level in the supplied power is lowered.Type: ApplicationFiled: August 3, 2001Publication date: March 14, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shiro Sakiyama, Jun Kajiwara, Masayoshi Kinoshita
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Patent number: 6307360Abstract: The switching regulator of a synchronous rectifying mode comprises the first and second switches SW1, SW2 arranged in series between the power source Vdd and the ground Vss, the switch control unit 1 which controls the on-off operation of the switches SW1, SW2, and the smoothing circuit 4 which smoothes the output node potential Vnd. When the signal Sc1 indicates that the output node potential Vnd goes below the first reference potential Vr1 which is the reference to detect the occurrence of the inrush current while the first switch SW1 is in the ON state, the control circuit 10 turns off the first switch SW1. Thus, the detection of the inrush current is conducted by making use of a voltage drop due to the on resistance of the first switch SW1, so that it is unnecessary to provide a resistance element for detecting the inrush current.Type: GrantFiled: October 23, 2000Date of Patent: October 23, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Jun Kajiwara, Shiro Sakiyama, Masayoshi Kinoshita, Katsuji Satomi, Katsuhiro Ootani
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Patent number: 6150800Abstract: A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source.Type: GrantFiled: September 15, 1999Date of Patent: November 21, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masayoshi Kinoshita, Shiro Sakiyama, Jun Kajiwara, Katsuji Satomi, Hiroo Yamamoto, Katsuhiro Ootani