Abstract: A semiconductor device includes a substrate, plugs, and interconnections. The plugs include a first plug and a second plug that are disposed above the substrate and extend in a first direction that crosses an upper surface of the substrate, and a third plug disposed above and electrically connected to the second plug and extending in the first direction. The interconnections include a first interconnection disposed above and electrically connected to the first plug, a second interconnection disposed below and electrically connected to the first plug, and a third interconnection disposed below and electrically connected to the second plug. The first interconnection contains copper. The third plug contains tungsten. An upper end of the second plug is different in level from an upper end of the first plug and a lower end of the second plug is same in level as a lower end of the first plug.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: According to one embodiment, in a semiconductor memory device including a first chip and a second chip. The first chip includes a first stacked body, a first semiconductor film, a second stacked body, a second semiconductor film, a contact plug and a first planar wiring line. The contact plug extends in the third direction between the first stacked body and the second stacked body. The first planar wiring line is disposed on a side opposite to the second chip with respect to the first stacked body, the contact plug, and the second stacked body, the first planar wiring line extending in the first direction and the second direction, covering at least the contact plug, and being connected to the contact plug.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: A support substrate according to an embodiment includes: a substrate having conductivity; a first insulating layer disposed on the substrate; a first layer having conductivity and disposed on the first insulating layer; a second insulating layer disposed on the first layer; a second layer having conductivity and disposed on the second insulating layer; a plurality of first plugs penetrating the first insulating layer and connecting the substrate and the first layer; and a plurality of second plugs penetrating the second insulating layer and connecting the first layer and the second layer.

Abstract: A semiconductor storage device includes transistors disposed on a substrate; a first metal wiring layer disposed over the transistors at a first position, the first metal wiring layer including a first metal wiring; a stacked body, disposed above the first metal wiring layer, including a first conductive layers and first insulating layers alternately stacked; a pillar including a semiconductor layer that includes a first type impurity in an upper end and penetrates through the stacked body; and a second conductive layer disposed at a second position further from the substrate than the first position, overlapped with the first metal wiring or another metal wiring in the first metal wiring layer, and not electrically connected to any of the transistors, the first conductive layers, or the first metal wiring layer. The second conductive layer has a higher melting point than the first metal wiring.

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

Abstract: In one embodiment, a semiconductor device includes a first interconnect including a first pad. The semiconductor device further includes a second pad provided on the first interconnect. In the semiconductor device, the second pad is in contact with another pad, and the first pad is not in contact with another pad.

Abstract: According to one embodiment, a semiconductor device includes a first chip with a first electrode and a second electrode and a second chip with a third electrode and a fourth electrode. The first and second chips are bonded to each other with the first electrode contacting the third electrode and the second electrode contacting the fourth electrode. A thickness of the first electrode in a first direction perpendicular to a bonding interface between the first chip and the second chip is less than a thickness of the second electrode in the first direction. A planar area of the first electrode at the bonding interface is greater than a planar area of the second electrode at the bonding interface.

Abstract: A memory device includes a substrate; first conductors aligned apart from each other in a first direction; a second conductor and a third conductor each extending in a second direction between the substrate and the first conductors, and being aligned apart from each other in the second direction; fourth conductors aligned apart from each other in the first direction on an opposite side of the substrate with respect to the first conductors; a fifth conductor extending in the second direction between the first conductors and the fourth conductors; and a first interconnect coupling between the fifth conductor and the substrate. The first interconnect includes a contact extending in the first direction and passing through the first conductors between the second and third conductors.

Abstract: According to one embodiment, a semiconductor storage device includes a first chip, a second chip, and a third chip. In the third chip, a first conductive film is above a first stacked body. The first conductive film extends across the first stacked body when viewed from a stacking direction. A first plug extends in the stacking direction and connects the first conductive film and a second conductive film. The first electrode is connected to the second conductive film. In the second chip, a third conductive film is above a second stacked body. A second plug extends in the stacking direction and connects the third conductive film and the fourth conductive film. The second electrode is connected to the fourth conductive film. The first chip has a first wiring structure therein. The first wiring structure is connected to the second electrode.

Abstract: A semiconductor memory device includes first and second chips. The first chip includes a first region and a second region. The first region includes memory cells, bit lines, word lines, and first bonding electrodes electrically connected to bit lines. The second region includes contacts electrically connected to word lines and second bonding electrodes electrically connected to contacts. The first bonding electrodes include a third bonding electrode and a fourth bonding electrode adjacent. The second bonding electrodes include a fifth bonding electrode and a sixth bonding electrode adjacent. A distance from a center position of the third bonding electrode to a center position of the fourth bonding electrode and a distance from a center position of the fifth bonding electrode to a center position of the sixth bonding electrode are matched in a range of from 90% to 110%.

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: A semiconductor storage device of an embodiment includes a substrate, a plurality of first conductive layers, pillar, and a second conductive layer. The plurality of first conductive layers are provided above the substrate, and mutually separated in a first direction. The pillar is provided to penetrate the plurality of the first conductive layers, and includes a first semiconductor layer extending in the first direction. A part of the pillar that intersects with the first conductive layers are functioned as memory cells. The second conductive layer is provided above the plurality of first conductive layers and is in contact with the first semiconductor layer. The second conductive layer is made of a metal or a silicide.

Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a first pad provided in the first insulator, and including first and second layers provided on lateral and lower faces of the first insulator in order. The device further includes a second insulator provided on the first insulator. The device further includes a second pad provided on the first pad in the second insulator, and including third and fourth layers provided on lateral and upper faces of the second insulator in order. The device further includes a first portion provided between an upper face of the first pad and a lower face of the second insulator or between a lower face of the second pad and an upper face of the first insulator, and including a metal element same as a metal element included in the first layer or the third layer.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.

Abstract: In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.

Abstract: In one embodiment, a semiconductor device includes a substrate, a first interconnection provided above the substrate, and a first pad provided on the first interconnection. The device further includes a second pad provided on the first pad, and a second interconnection provided on the second pad. Furthermore, the first pad includes a first layer provided in a first insulator above the substrate, and a second layer that is provided in the first insulator via the first layer and is in contact with the first interconnection, or the second pad includes a third layer provided in a second insulator above the substrate, and a fourth layer that is provided in the second insulator via the third layer and is in contact with the second interconnection.