Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

Abstract: A semiconductor device includes: a plurality of first electrode films stacked in a state of being insulated from each other; a plurality of semiconductor members extending in a stacked direction of the plurality of first electrode films in a stacked body of the plurality of first electrode films; a plurality of charge storage members provided between the plurality of first electrode films and the plurality of semiconductor members; a first conductive film having a first surface, and commonly connected to the plurality of semiconductor members on the first surface; a first insulating film provided on a second surface of the first conductive film on the side opposite to the first surface; a contact provided in the first insulating film and connected to the first conductive film; and a second conductive film provided on the first insulating film and connected to the contact.

Abstract: In one embodiment, a semiconductor device includes a substrate, a plurality of transistors provided on the substrate. The device further includes a first interconnect layer provided above the transistors and electrically connected to at least one of the transistors, one or more first plugs provided on the first interconnect layer, and a first pad provided on the first plugs. The device further includes a second pad provided on the first pad, one or more second plugs provided on the second pad, and a second interconnect layer provided on the second plugs. The device further includes a memory cell array provided above the second interconnect layer and electrically connected to the second interconnect layer. A number of the second plugs on the second pad is larger than a number of the first plugs under the first pad.

Abstract: In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.

Abstract: In one embodiment, a semiconductor device includes a substrate, a first interconnection provided above the substrate, and a first pad provided on the first interconnection. The device further includes a second pad provided on the first pad, and a second interconnection provided on the second pad. Furthermore, the first pad includes a first layer provided in a first insulator above the substrate, and a second layer that is provided in the first insulator via the first layer and is in contact with the first interconnection, or the second pad includes a third layer provided in a second insulator above the substrate, and a fourth layer that is provided in the second insulator via the third layer and is in contact with the second interconnection.

Abstract: In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: In one embodiment, a semiconductor device includes a substrate, a plurality of transistors provided on the substrate. The device further includes a first interconnect layer provided above the transistors and electrically connected to at least one of the transistors, one or more first plugs provided on the first interconnect layer, and a first pad provided on the first plugs. The device further includes a second pad provided on the first pad, one or more second plugs provided on the second pad, and a second interconnect layer provided on the second plugs. The device further includes a memory cell array provided above the second interconnect layer and electrically connected to the second interconnect layer. A number of the second plugs on the second pad is larger than a number of the first plugs under the first pad.

Abstract: A semiconductor device includes a substrate, a logic circuit provided on the substrate, a wiring layer including a plurality of wirings that are provided above the logic circuit, a first insulating film below the wiring layer, a plug, and a second insulating film. Each of the wirings contains copper and extends along a surface plane of the substrate in a first direction. The wirings are arranged along the surface plane of the substrate in a second direction different from the first direction. The plug extends through the first insulating film in a third direction crossing the first and second directions and is electrically connected to one of the wirings. The plug contains tungsten. The second insulating film is provided between the first insulating film and the plug.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.

Abstract: According to an embodiment, a template includes a flat plate-shaped first member, a flat plate-shaped second member including a pattern arrangement face, and a flat plate-shaped third member provided with an opening at a position corresponding to an arrangement position of the second member. The template is dividable at a position of at least one of a first boundary between the first member and the second member and a second boundary between the first member and the third member.

Abstract: An integrated circuit device includes a first insulating film, a second insulating film provided on the first insulating film, and having a composition different from a composition of the first insulating film, a first interconnect extending in a first direction crossing a vertical direction, and having a lower portion disposed in the first insulating film, and an upper portion disposed in the second insulating film, and a second interconnect extending in the first direction, and having a lower portion disposed in the first insulating film, and an upper portion disposed in the second insulating film. An air gap is formed in the first insulating film and in the second insulating film and also between the first interconnect and the second interconnect. A lower end of the air gap is located lower than a lower surface of the first interconnect and a lower surface of the second interconnect.

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an insulating film, a first interconnect, a conductor, and a frame-shaped portion. The insulating film is provided on the semiconductor layer. The first interconnect is provided on the insulating film. The conductor extends through the insulating film and electrically connects the semiconductor layer and the first interconnect. The frame-shaped portion extends through the insulating film and is provided in a second region different from a first region, the conductor being provided in the first region. The frame-shaped portion protrudes from a surface of the insulating film on which the first interconnect is provided.

Abstract: In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.

Abstract: In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.