Patents by Inventor Masayuki Katagiri

Masayuki Katagiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240122202
    Abstract: The invention provides a chocolate having strong aroma characteristics. The aroma characteristics may include at least one of a fruity aroma and a floral aroma, and isoamyl acetate may be contained as an aroma component. The invention also provides a novel method for producing a chocolate having strong aroma characteristics. The method includes a step of crushing at least a cacao raw material and a sugar raw material in a sealed crusher.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 18, 2024
    Applicant: MEIJI CO., LTD.
    Inventors: Takashi KATAGIRI, Masayuki SATO, Keisuke KIMURA, Noriyuki MANADA
  • Publication number: 20230383047
    Abstract: Provided is a resin composition comprises a cyanate ester compound (A), an amine adduct compound (B) and a borate ester (C).
    Type: Application
    Filed: March 9, 2023
    Publication date: November 30, 2023
    Inventors: Kousuke IKEDA, Yoshihiro YASUDA, Masayuki KATAGIRI
  • Publication number: 20230096312
    Abstract: Provided is a resist composition which contains a resin (A) and a solvent (B) that contains a compound (B1) represented by general formula (b-1), wherein the content of the active ingredients based on the total amount of the resist composition is 45% by mass or less. (In formula (b-1), R1 represents an alkyl group having from 1 to 10 carbon atoms.
    Type: Application
    Filed: February 17, 2021
    Publication date: March 30, 2023
    Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Takumi OKADA, Hideyuki SATO, Masayuki KATAGIRI, Shu SUZUKI
  • Patent number: 11374141
    Abstract: A solar cell assembly includes a plurality of solar cells and an inter-cell region provided between adjacent ones of the solar cells included in the plurality of solar cells. Each of the solar cells and the inter-cell region includes: a semiconductor substrate having a first conductivity type and having a first main surface and a second main surface that face away from each other; a first amorphous semiconductor layer having a second conductivity type and being provided on a first main surface side of the semiconductor substrate; an insulating layer provided on part of the first amorphous semiconductor layer; and a first transparent conductive film provided on the first amorphous semiconductor layer so as to cover the insulating layer. In a plan view of the solar cell assembly, the insulating layer is provided along the inter-cell region and partially overlapping the inter-cell region.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 28, 2022
    Assignee: PANASONIC HOLDINGS CORPORATION
    Inventors: Toshiyuki Sakuma, Kazuya Murata, Masayuki Katagiri, Akiyoshi Ogane, Akinao Kitahara
  • Publication number: 20200313020
    Abstract: A solar cell assembly includes a plurality of solar cells and an inter-cell region provided between adjacent ones of the solar cells included in the plurality of solar cells. Each of the solar cells and the inter-cell region includes: a semiconductor substrate having a first conductivity type and having a first main surface and a second main surface that face away from each other; a first amorphous semiconductor layer having a second conductivity type and being provided on a first main surface side of the semiconductor substrate; an insulating layer provided on part of the first amorphous semiconductor layer; and a first transparent conductive film provided on the first amorphous semiconductor layer so as to cover the insulating layer. In a plan view of the solar cell assembly, the insulating layer is provided along the inter-cell region and partially overlapping the inter-cell region.
    Type: Application
    Filed: March 27, 2020
    Publication date: October 1, 2020
    Inventors: Toshiyuki SAKUMA, Kazuya MURATA, Masayuki KATAGIRI, Akiyoshi OGANE, Akinao KITAHARA
  • Publication number: 20200255575
    Abstract: The present invention provides a novel cyanic acid ester compound that has excellent solvent solubility and provides a cured product having a low rate of thermal expansion and having excellent flame retardance and heat resistance, and a resin composition containing the compound, etc. The present invention provides a resin composition whose cured product obtained by curing can achieve a printed circuit board excellent in peel strength, glass transition temperature, rate of thermal expansion, rate of water absorption, and thermal conductivity. The present invention provides a resin composition whose cured product obtained by curing can achieve a printed circuit board not only having a high glass transition temperature and low thermal expansibility but being also excellent in flexural modulus and thermal conductivity.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Shota KOGA, Kentaro TAKANO, Masayuki KATAGIRI, Yoshihiro YASUDA, Tomoo TSUJIMOTO
  • Patent number: 10741443
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 11, 2020
    Assignee: Kioxia Corporation
    Inventors: Masayuki Kitamura, Atsuko Sakata, Makoto Wada, Yuichi Yamazaki, Masayuki Katagiri, Akihiro Kajita, Tadashi Sakai, Naoshi Sakuma, Ichiro Mizushima
  • Patent number: 10580737
    Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 3, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Yasutaka Nishida, Takashi Yoshida, Yuichi Yamazaki, Masayuki Katagiri, Naoshi Sakuma
  • Publication number: 20190259707
    Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi Sakai, Yasutaka Nishida, Takashi Yoshida, Yuichi Yamazaki, Masayuki Katagiri, Naoshi Sakuma
  • Publication number: 20190259659
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki KITAMURA, Atsuko Sakata, Makoto Wada, Yuichi Yamazaki, Masayuki Katagiri, Akihiro Kajita, Tadashi Sakai, Naoshi Sakuma, Ichiro Mizushima
  • Patent number: 10370325
    Abstract: The present invention provides a novel cyanate ester compound which has excellent solvent solubility and from which a hardened product having a low coefficiency of thermal expansion and excellent flame retardancy and heat resistance is obtained. The present invention is a cyanate ester compound obtained by cyanating a naphthol-dihydroxynaphthalene aralkyl resin or a dihydroxynaphthalene aralkyl resin.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: August 6, 2019
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Masayuki Katagiri, Tatsuya Shima, Keita Tokuzumi
  • Patent number: 10325805
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 18, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Kitamura, Atsuko Sakata, Makoto Wada, Yuichi Yamazaki, Masayuki Katagiri, Akihiro Kajita, Tadashi Sakai, Naoshi Sakuma, Ichiro Mizushima
  • Patent number: 10325851
    Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 18, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Yasutaka Nishida, Takashi Yoshida, Yuichi Yamazaki, Masayuki Katagiri, Naoshi Sakuma
  • Publication number: 20190112410
    Abstract: The present invention provides a novel cyanic acid ester compound that has excellent solvent solubility and provides a cured product having a low rate of thermal expansion and having excellent flame retardance and heat resistance, and a resin composition containing the compound, etc. The present invention provides a resin composition whose cured product obtained by curing can achieve a printed circuit board excellent in peel strength, glass transition temperature, rate of thermal expansion, rate of water absorption, and thermal conductivity. The present invention provides a resin composition whose cured product obtained by curing can achieve a printed circuit board not only having a high glass transition temperature and low thermal expansibility but being also excellent in flexural modulus and thermal conductivity.
    Type: Application
    Filed: March 27, 2017
    Publication date: April 18, 2019
    Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Shota KOGA, Kentaro TAKANO, Masayuki KATAGIRI, Yoshihiro YASUDA, Tomoo TSUJIMOTO
  • Patent number: 10174149
    Abstract: The present invention provides a cyanic acid ester compound having a structure represented by the following general formula (1): wherein n represents an integer of 1 or larger.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 8, 2019
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Takashi Kobayashi, Kentaro Takano, Masayuki Katagiri, Keita Tokuzumi, Tatsuya Shima
  • Patent number: 10160824
    Abstract: The cyanate ester compound of the present invention is obtained by cyanating a modified naphthalene formaldehyde resin.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: December 25, 2018
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Masayuki Katagiri, Go Higashihara, Kenji Arii, Yuuichi Sugano, Makoto Tsubuku
  • Patent number: 10155835
    Abstract: To provide a novel cyanate ester compound that can realize a cured product having low dielectric constant and dielectric loss tangent, and excellent flame retardancy and heat resistance, and moreover has relatively low viscosity, excellent solvent solubility, and also excellent handling properties, and a method for producing the cyanate ester compound, and a curable resin composition and the like using the cyanate ester compound. A phenol-modified xylene formaldehyde resin is cyanated.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 18, 2018
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Yuuichi Sugano, Masayuki Katagiri, Seiji Kita, Daisuke Ohno, Masanobu Sogame
  • Publication number: 20180277487
    Abstract: A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.
    Type: Application
    Filed: August 30, 2017
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi SAKAI, Yasutaka NISHIDA, Takashi YOSHIDA, Yuichi YAMAZAKI, Masayuki KATAGIRI, Naoshi SAKUMA
  • Publication number: 20180269157
    Abstract: A wiring of an embodiment includes: a multilayer graphene including graphene sheets laminated in a first direction, the multilayer graphene extended in a second direction regarded as a longitudinal direction that intersects with the first direction; a first metal part in direct contact with the multilayer graphene; a second metal part spaced apart from the first metal part in the second direction, the second metal part in direct contact with the multilayer graphene; a first conductive part disposed on the multilayer graphene in the first direction, and electrically connected to the multilayer graphene with the first metal part interposed therebetween; and a second conductive part disposed on the multilayer graphene in the first direction, and electrically connected to the multilayer graphene with the second metal part interposed therebetween.
    Type: Application
    Filed: September 1, 2017
    Publication date: September 20, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki KATAGIRI, Tatsuro SAITO, Tadashi SAKAI, Hisao MIYAZAKI
  • Patent number: 9997611
    Abstract: A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 12, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Masayuki Katagiri, Yuichi Yamazaki