Abstract: A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

Abstract: Disclosed is a semiconductor device in which a circuit in the semiconductor chip is divided into a plurality of sub-circuits. The semiconductor device includes switches between the respective sub-circuits and a power supply, and a circuit that variably controls on-resistances of the switches 111 to 11N.

Abstract: An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information.

Abstract: A redundant computing system is composed of two systems: a first arithmetic processing unit (A-system) and a second arithmetic processing unit (B-system) having the same functions. A diagnosis control unit performs diagnosis of one system while the other system is performing arithmetic processing operation. The diagnosis control unit controls the input to the first and second arithmetic processing units by way of an input control unit according to the diagnosis operation, and an output control unit controls the output from the first and second arithmetic processing units according to the diagnosis result. After termination of the diagnosis, a value is copied from a storage unit of the system which has not been diagnosed to a storage unit of the system which has been diagnosed, and the redundant computing system resumes the redundant operation.

Abstract: A main chip has a signal processing circuit for executing signal processing; a plurality of signal transmitting circuits for transmitting signals between the signal processing circuit and a signal transmitting circuit; and a control circuit for controlling operation/non-operation of the signal transmitting circuits in accordance with signal processing content of the signal processing circuit. Functional chips each have a signal processing circuit for executing auxiliary signal processing different from that of the signal processing circuit; and one or a plurality of signal transmitting circuits for transmitting signals between the signal processing circuit and the signal transmitting circuits. The main chip and the functional chips are stacked. The signal transmitting circuits and the signal transmitting circuit are non-contact-type signal transmitting circuits utilizing inductive coupling and are arranged so as to overlap when viewed from the stacking direction.

Abstract: A clock converting circuit (1) receives and then converts m-phase clocks of a frequency f having a phase difference of 1/(f×m) to n-phase clocks of the frequency f having a phase difference of 1/(f×n). A single-phase clock generating circuit (2) receives the n-phase clocks of the frequency f having a phase difference equivalent time of 1/(f×n) to generate single-phase clocks in synchronism with the rising or falling edges of the n-phase clocks. Since the frequency of the m-phase clocks inputted to the clock converting circuit (1) is ‘f’, if a desired frequency of the single-phase clocks is decided, then ‘n’ can be obtained from the equation: the frequency of the single-phase clocks is equal to (f×n). This value of ‘n’ is set to the clock converting circuit (1), thereby obtaining the n-phase clocks of the frequency f from the m-phase clocks of the frequency f to provide single-phase clocks of a desired frequency.

Abstract: There is provided an aging diagnostic device including: a reference ring oscillator (101) that constitutes a ring oscillator using an odd-numbered plurality of logic gates constituted using a CMOS circuit; a test ring oscillator (102) that constitutes a ring oscillator using an odd-numbered plurality of logic gates having the same configuration as that of the logic gate; a load unit (104) that inputs a load signal to the test ring oscillator (102); a control unit (105) that simultaneously inputs a control signal instructing a start of oscillation of the reference ring oscillator (101) and the test ring oscillator (102) to the reference ring oscillator (101) and the test ring oscillator (102); and a comparison unit (103) that compares differences in the amount of movement of pulses within the reference ring oscillator (101) and the test ring oscillator (102), respectively, in the same time.

Abstract: A semiconductor device comprising a signal transmission line of a microstrip structure, capable of increasing the characteristic impedance of the signal transmission line and reducing coupling between a plurality of signal lines. In a signal transmission line of a microstrip structure composed of a signal line and a ground plate, the capacitance between wires is reduced and the characteristic impedance can be increased by forming holes in the signal line or in the ground plate. The coupling between a plurality of signal lines can also be reduced.

Abstract: A semiconductor integrated circuit comprising a processor having an output signal of instruction log information and being operable in a program in memory is disclosed. The semiconductor integrated circuit comprises trace determination circuit for comparing an instruction code that corresponds to the instruction log information from a processor with an instruction code that is read from the memory to detect faults.

Abstract: Provided is a wireless communication system including a first radio equipment that transmits first data using first radio waves, a data transmitter that outputs a second radio wave generated by modulating the first radio wave according to second data to be transmitted, and a second radio equipment that receives the first radio wave and the second radio wave, and separates and demodulates the first data transmitted from the first radio equipment and the second data transmitted from the data transmitter contained in the received radio waves.

Abstract: A heat shield plate for a substrate annealing apparatus is provided with a horizontally supported flat-plate-like substrate 1, a heater 5 positioned above the substrate to heat the upper surface of the substrate with radiation heat, and a heat shield plate 10 horizontally movable between a shielding position where the substrate is shielded from heater and an open position out of the shielding position. The heat shield plate 10 is composed of a structural member 12 made of a low thermal expansion material (carbon composite material) which is hardly deformed due to a temperature difference in the shielding position, and a heat insulating member 14 which covers the upper surface of the structural member and keeps the surface at an allowable temperature or below.

Abstract: Disclosed is a test circuit including a first transfer circuit, a second transfer circuit and comparators and performing parallel testing of a plurality of chips under test. The first transfer circuit includes flip-flops. A data pattern from a tester is supplied to the initial stage chip under test. To the remaining chips under test, output data from the corresponding stages of the first transfer circuit are supplied. The second transfer circuit sequentially transfers an output of the initial stage chip under test, as an expected value pattern, in response to clock cycles. The comparator compares output data of the chip under test with an expected value pattern from the corresponding stage of the second transfer circuit.

Abstract: To provide, for example, a pulse input type power amplifying apparatus that can be operated at low voltage and low power, effectively suppressing generation of harmonic component. The amplifying apparatus includes at least two amplification circuits, one and other amplification circuits, composed of multiple amplifiers whose output sides are connected to each other, driven at the same frequency. The multiple amplifiers forming the one amplification circuit are configured with a first inverting amplifier M12 inputting and amplifying a reference pulse, and a second inverting amplifier M11 to which an inverted pulse formed by shifting and inverting the phase of the reference pulse is inputted. The other amplification circuit is configured with the first inverting amplifier M14 and the second inverting amplifier M13 to each of which other wide pulse with a width greater than that of the reference pulse is commonly inputted.

Abstract: An electronic circuit includes: a first power line capable of supplying power; a second power line capable of supplying power independently from the first power line; a main circuit connected to the second power line; a detector that detects the supply of power from the first power line or the second power line; and a controller connected to the first power line and the second power line, wherein the controller controls a voltage or a current supplied from the first power line and supplies the voltage or the current to the main circuit when the detector detects supply of power from the first power line.

Abstract: An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit.

Abstract: It is possible to provide a circuit and method for carrying out a parallel test using BOST (Built Out Self Test). The circuit includes first transfer circuits (11-1, 11-2, . . . ) that extract a data pattern supplied to a complete operating article chip (10) in a BOST (3) from the BOST and that successively transmit the data pattern in response to a clock signal, and second transfer circuits (12-1, 12-2, . . . ) that extract output data from the complete operating article chip (10) as an expectation value pattern and that successively transmit the expectation value pattern in response to the clock signal. The data pattern supplied to the complete operating article chip (10) is applied to one chip to be measured (10-1) and the data pattern from a corresponding stage of the first transfer circuits (11-1, 11-2, . . . ) is applied to each of other chips to be measured (10-2, . . . ).

Abstract: A programmable semiconductor device has a switch element in an interconnection layer, wherein in at least one of the inside of a via, interconnecting a wire of a first interconnection layer and a wire of a second interconnection layer, a contact part of the via with the wire of the first interconnection layer and a contact part of the via with the wire of the second interconnection layer, there is provided a variable electrical conductivity member, such as a member of an electrolyte material. The via is used as a variable electrical conductivity type switch element or as a variable resistance device having a contact part with the wire of the first interconnection layer as a first terminal and having a contact part with the wire of the second interconnection layer as a second terminal.

Abstract: Disclosed is a clock adjusting circuit comprising a phase shifter that receives a clock signal and variably shifts, based on a control signal, respective timing phases of a rising edge and a falling edge of the clock signal; and a control circuit that supplies the control signal to the phase shifter circuit before each edge is output; wherein the clock signal, in which at least one of a period, a duty ratio, jitter and skew/delay of the input clock signal is changed over an arbitrary number of clock cycles, is output.

Abstract: A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).

Abstract: A light receiving circuit (114) includes a light inputting circuit (113) which converts one-system optical signal to be outputted from an optical transmission path (101) to an electrical signal and inverts a potential of the electrical signal each time the optical signal is detected, and a buffer circuit (110) which amplifies the electrical signal converted by the light inputting circuit and outputs the same. According to such configuration, since one-system optical signal may be inputted to the light receiving circuit, a system circuit configuration can be avoided to be complicated.