Abstract: Provided is a modulation device including a signal selection circuit selecting two carrier signals from a plurality of carrier signals having the same frequency and the same phase difference according to a defined control signal and outputting the selected carrier signals, and a phase interpolator adjusting the phase in smaller units than the phase difference between the plurality of carrier signals according to the control signal and modulating the frequency or the phase of the carrier signal into a baseband signal based on the carrier signals selected by the signal selection circuit to generate a carrier wave signal.

Abstract: A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

Abstract: A semiconductor integrated circuit comprising a processor having an output signal of instruction log information and being operable in a program in memory is disclosed. The semiconductor integrated circuit comprises trace determination circuit for comparing an instruction code that corresponds to the instruction log information from a processor with an instruction code that is read from the memory to detect faults.

Abstract: In a program circuit that can reduce exhaustion of a switching element that uses oxidation-reduction reactions of an electrolyte material, a voltage source (106) applies voltage to a switching element (100), a measurement circuit (107) measures a parameter that changes in accordance with the resistance value of the switching element (100), and a control circuit (104) causes the voltage source (106) to apply voltage to the switching element (100) while progressively increasing the voltage. The control circuit (104) further causes the voltage source (106) to halt the application of voltage when the parameter measured by the measurement circuit (107) reaches a prescribed value.

Abstract: A segment-type friction material has blocks each composed of four segment pieces. Five blocks are stuck by adhesion to a core metal 2 along an entire circumference thereof so as to constitute one surface of the segment-type friction material. Gaps are provided between the five blocks to form oil grooves that make an automatic transmission fluid (ATF) to flow. Five oil grooves are formed in total on one surface as a whole of the segment-type friction material.

Abstract: A molding apparatus of a wet friction material has a pair of guide posts vertically extending on a molding apparatus main body. The pair of the guide posts passes through fifteen stages (sixteen pieces) of molding dies. A pair of pantograph-type open-close mechanisms is attached to opposite side surfaces of the molding dies. Thus, the molding dies are piled up on each other so as to come near to each other (mold clamping) and move apart from each other (mold opening). With the pantograph-type open-close link mechanism, all the molding dies are opened and closed at the same time. If the molding dies are slid at a speed of 200 mm/sec, it takes only 3.75 seconds (50 mm*15/200 mm=3.75 sec). It takes a double of that time or 7.5 seconds, that is a half of the time of a related art.

Abstract: Even if a multiprocessor includes an uneven performance core, an inoperative core or a core that does not satisfy such a performance as designed but if the contrivance of task allocation can satisfy the requirement of an application to be executed, the multiple processors are shipped. In a task group allocation method for allocating, to a processor having a plurality of cores, task groups included in an application for the processor to execute, a calculation section measures performances and disposition patterns of the cores, generates a restricting condition associating the measured performances and disposition patterns of the cores with information indicating whether the application can be executed, and, with reference to the restricting condition, reallocates to the cores, the task groups that have previously been allocated to the cores.

Abstract: The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B.

Abstract: Spectrum measurement circuit (101) includes: N- (where N is integer equal or greater than 2) phase clock generation circuit (304) for supplying phase-modulated signals in which the phase of a clock signal is shifted by a phase modulation amount each time the settings of the phase modulation amount are switched; mixer circuit (303) for taking the product of a measured signal supplied from a transmitter and the phase-modulated signals supplied from N-phase clock generation circuit (304); average value output circuit (305) for supplying an average voltage value of the output signal of mixer circuit (303); memory (307) for storing the average voltage value supplied from average value output circuit (305) for each phase modulation amount of the N-phase clock generation circuit (304); and arithmetic unit (308) for using the average voltage value for each phase modulation amount of N-phase clock generation circuit (304) to calculate the signal strength of the measured signal.

Abstract: An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information.

Abstract: Disclosed is a semiconductor device in which a circuit in the semiconductor chip is divided into a plurality of sub-circuits. The semiconductor device includes switches between the respective sub-circuits and a power supply, and a circuit that variably controls on-resistances of the switches 111 to 11N.

Abstract: A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit.

Abstract: [PROBLEMS] To provide, for example, a pulse input type power amplifying apparatus that can be operated at low voltage and low power, effectively suppressing generation of harmonic component. [MEANS FOR SOLVING THE PROBLEMS] The amplifying apparatus includes at least two amplification circuits, one and other amplification circuits, composed of multiple amplifiers whose output sides are connected to each other, driven at the same frequency. The multiple amplifiers forming the one amplification circuit are configured with a first inverting amplifier M12 inputting and amplifying a reference pulse, and a second inverting amplifier M11 to which an inverted pulse formed by shifting and inverting the phase of the reference pulse is inputted. The other amplification circuit is configured with the first inverting amplifier M14 and the second inverting amplifier M13 to each of which other wide pulse with a width greater than that of the reference pulse is commonly inputted.

Abstract: Disclosed is a test circuit including a first transfer circuit, a second transfer circuit and comparators and performing parallel testing of a plurality of chips under test. The first transfer circuit includes flip-flops. A data pattern from a tester is supplied to the initial stage chip under test. To the remaining chips under test, output data from the corresponding stages of the first transfer circuit are supplied. The second transfer circuit sequentially transfers an output of the initial stage chip under test, as an expected value pattern, in response to clock cycles. The comparator compares output data of the chip under test with an expected value pattern from the corresponding stage of the second transfer circuit.

Abstract: It is possible to provide a circuit and method for carrying out a parallel test using BOST (Built Out Self Test). The circuit includes first transfer circuits (11-1, 11-2, . . . ) that extract a data pattern supplied to a complete operating article chip (10) in a BOST (3) from the BOST and that successively transmit the data pattern in response to a clock signal, and second transfer circuits (12-1, 12-2, . . . ) that extract output data from the complete operating article chip (10) as an expectation value pattern and that successively transmit the expectation value pattern in response to the clock signal. The data pattern supplied to the complete operating article chip (10) is applied to one chip to be measured (10-1) and the data pattern from a corresponding stage of the first transfer circuits (11-1, 11-2, . . . ) is applied to each of other chips to be measured (10-2, . . . ).

Abstract: [Problems] to provide a CMOS low-noise amplification circuit which can reduce a chip area and design time, and which is easy to be digital-controlled from outside. [Means For Solving the Problems] The amplification circuit includes; an amplification stage (12) which amplifies an input signal up to an intended value; a sample and hold circuit (13) which samples the output signal from the amplification stage (12) by sampling the output signal with a sampling frequency which is at least twice the frequency band of the output signal to convert the output signal to a discrete time signal; a moving average calculation unit (15) which selects and outputs a particular frequency from the discrete time signal outputted from the sample and hold circuit (13) by a moving average operation; and a smoothing filter (17) which smoothes the output signal from the moving average calculation unit (15) and feed it back to the input of the amplification stage (12).

Abstract: Disclosed is a clock adjusting circuit comprising a phase shifter that receives a clock signal and variably shifts, based on a control signal, respective timing phases of a rising edge and a falling edge of the clock signal; and a control circuit that supplies the control signal to the phase shifter circuit before each edge is output; wherein the clock signal, in which at least one of a period, a duty ratio, jitter and skew/delay of the input clock signal is changed over an arbitrary number of clock cycles, is output.

Abstract: A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.

Abstract: A main chip has a signal processing circuit for executing signal processing; a plurality of signal transmitting circuits for transmitting signals between the signal processing circuit and a signal transmitting circuit; and a control circuit for controlling operation/non-operation of the signal transmitting circuits in accordance with signal processing content of the signal processing circuit. Functional chips each have a signal processing circuit for executing auxiliary signal processing different from that of the signal processing circuit; and one or a plurality of signal transmitting circuits for transmitting signals between the signal processing circuit and the signal transmitting circuits. The main chip and the functional chips are stacked. The signal transmitting circuits and the signal transmitting circuit are non-contact-type signal transmitting circuits utilizing inductive coupling and are arranged so as to overlap when viewed from the stacking direction.

Abstract: A semiconductor device comprising a signal transmission line of a microstrip structure, capable of increasing the characteristic impedance of the signal transmission line and reducing coupling between a plurality of signal lines. In a signal transmission line of a microstrip structure composed of a signal line and a ground plate, the capacitance between wires is reduced and the characteristic impedance can be increased by forming holes in the signal line or in the ground plate. The coupling between a plurality of signal lines can also be reduced.