Abstract: A clock recovery circuit includes a phase discriminating circuit for discriminating, at every edge of a received data signal, phase lead or phase lag of an identically directed edge of the clock signal, and outputting the phase discrimination signal; an edge detecting circuit for detecting edges of the received data signal, outputting an edge detection signal of a fixed pulse width, delaying the received data signal and outputting the delayed signal; an exclusive-OR gate for outputting, as an edge injection signal, an exclusive-OR signal between the phase discrimination signal and delayed signal; and a voltage-controlled oscillator for variably controlling frequency of ring oscillation, injecting the edge injection signal into the loop of ring oscillation, and outputting a clock signal locked to the received data signal.

Abstract: A segment-type friction material has blocks each composed of four segment pieces. Five blocks are stuck by adhesion to a core metal 2 along an entire circumference thereof so as to constitute one surface of the segment-type friction material. Gaps are provided between the five blocks to form oil grooves that make an automatic transmission fluid (ATF) to flow. Five oil grooves are formed in total on one surface as a whole of the segment-type friction material.

Abstract: A semiconductor device comprising a signal transmission line of a microstrip structure, capable of increasing the characteristic impedance of the signal transmission line and reducing coupling between a plurality of signal lines. In a signal transmission line of a microstrip structure composed of a signal line and a ground plate, the capacitance between wires is reduced and the characteristic impedance can be increased by forming holes in the signal line or in the ground plate. The coupling between a plurality of signal lines can also be reduced.

Abstract: The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.

Abstract: A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

Abstract: A wet-type segmented friction material has a tape-like friction material substrate which is passed through and pressed between a roller having a dent at a center and a flat roller. At the same time, the friction material substrate is heated from an inside and an outside of the rollers so as to carry out a heat press compression processing. Then, a processed friction material substrate has a predetermined cross-section. The processed friction material substrate is cut into segment pieces each having a segment shape by a rotary push cutter having a sharp cutting edge. A cut position of the segment piece is selected such that two straight lines at two lateral sides of the segment shape is located within an area of a compressed portion of the processed friction material substrate. That is, a stepped or sunken compressed portion is provided on both sides of the segment piece.

Abstract: An objective is to provide a semiconductor integrated circuit apparatus capable of analyzing factors that exert an influence upon an actual operation of a semiconductor integrated circuit that is actually working, and further of reducing its factors. A semiconductor integrated circuit that is an object of measurement, and a measurement circuit for measuring a physical amount, which exerts an influence upon the actual operation of the semiconductor integrated circuit, such as jitter or noise jitter, and noise of this semiconductor integrated circuit are configured on an identical chip. Also, a measurement result of the measurement circuit of the present invention is analyzed, and is fed back to a circuit for adjusting the semiconductor integrated circuit that is an object of measurement.

Abstract: An optical-disc recording apparatus records an information signal on a loaded optical disc by emitting a laser beam towards the optical disc. The apparatus includes a detector that detects a characteristic of the optical disc based on a predetermined value obtained from light reflected from the optical disc; a laser-beam emitter that emits the laser beam towards the optical disc; a laser-beam driver that supplies a laser-beam driving signal to the laser-beam emitter; a power source that supplies a driving power to the laser-beam driver; and a controller that adjusts a voltage of the driving power supplied to the laser-beam driver in accordance with the detected characteristic of the optical disc.

Abstract: In manufacturing a segment-type wet friction material, each segment piece in a guide is pushed out and mounted on a rotating plate. Cut portions at opposite outer peripheral corners of the segment piece are fitted and engaged with two positioning pins so as to position the segment piece on the rotating plate. The segment piece is sucked by a pair of positioning suction holes located thereunder so as to be fastened. The rotating plate is turned 18 degrees and such operation is repeated until twenty segment piece are charged in a ring shape. Then, each two suction heads of a sucking/moving mechanism sucks surfaces of each segment piece. At the same time, a sucking operation of the positioning suction holes is stopped. Then, the twenty segment pieces arranged in the ring shape is lifted by the sucking/moving mechanism and moved in parallel to a core metal with an adhesive coated on an entire surface thereof. The twenty segment pieces are pressed to the core metal so as to adhere thereto.

Abstract: A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.

Abstract: In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.

Abstract: The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.

Abstract: A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

Abstract: An objective is to provide a semiconductor integrated circuit apparatus capable of analyzing factors that exert an influence upon an actual operation of a semiconductor integrated circuit that is actually working, and further of reducing its factors. A semiconductor integrated circuit that is an object of measurement, and a measurement circuit for measuring a physical amount, which exerts an influence upon the actual operation of the semiconductor integrated circuit, such as jitter or noise jitter, and noise of this semiconductor integrated circuit are configured on an identical chip. Also, a measurement result of the measurement circuit of the present invention is analyzed, and is fed back to a circuit for adjusting the semiconductor integrated circuit that is an object of measurement.

Abstract: A semiconductor integrated circuit is disclosed for enabling faster operations than a clock frequency using multi-phase clocks, A clock generator circuit generates multi-phase clocks comprised of a plural-phase clocks which are the same in clock frequency but different in phase from one another. A clock distributor distributes the multi-phase clocks generated by the clock generator circuit within the integrated circuit. A logic circuit operates at an operating frequency higher than the clock frequency in synchronization with the multi-phase clocks generated by the clock generator circuit and distributed by the clock distributor.

Abstract: A programmable semiconductor device has a switch element in an interconnection layer, wherein in at least one of the inside of a via, interconnecting a wire of a first interconnection layer and a wire of a second interconnection layer, a contact part of the via with the wire of the first interconnection layer and a contact part of the via with the wire of the second interconnection layer, there is provided a variable electrical conductivity member, such as a member of an electrolyte material. The via is used as a variable electrical conductivity type switch element or as a variable resistance device having a contact part with the wire of the first interconnection layer as a first terminal and having a contact part with the wire of the second interconnection layer as a second terminal.

Abstract: An interconnect circuit transmits data signals from a first terminal to a second terminal through a data line having a plurality of data driving circuits capable of temporarily interrupting or reestablishing data transmission in a portion of the data line responsive to congestion signals which propagate along a congestion line in a direction opposite the direction of data signal transmission. The congestion signals may be indicative of the status of the second terminal, where a first congestion signal may indicate the second terminal is not receiving data and a second congestion signal may indicate the second terminal is receiving data. Different types of data driving circuits may be cascade-connected in an alternating fashion and may be adapted to interrupt or to reestablish data transmission in sequence starting from the data driving circuit nearest the second terminal of the interconnect and continuing in the direction of the first terminal.

Abstract: To assure good data playback characteristics even when reading data from a magnetic tape having recording tracks at a narrow pitch, a data recording and/or reproducing apparatus is provided which includes a tape feeder 7 to feed a magnetic tape 100 in which data is recorded on recording tracks formed obliquely to the moving direction of the magnetic tape 100, a magnetic head 4 including a playback head having a width smaller than the recording width of the recording tracks to read data from the magnetic tape 100 and a record head to write data to the magnetic tape 100, a rotating drum 5 on which the magnetic tape 100 is scanned by the magnetic head 4, a rotating drum controller 6 to allow the playback head to scan the recording tracks at least two times in order to detect data recorded in the magnetic tape 100, and a read signal processor 3 to reproduce data recorded in the magnetic tape 100 from the data detected by the playback head having been allowed by the rotating drum controller 6 to scan the recording

Abstract: A wet-type segmented friction material has a tape-like friction material substrate which is passed through and pressed between a roller having a dent at a center and a flat roller. At the same time, the friction material substrate is heated from an inside and an outside of the rollers so as to carry out a heat press compression processing. Then, a processed friction material substrate has a predetermined cross-section. The processed friction material substrate is cut into segment pieces each having a segment shape by a rotary push cutter having a sharp cutting edge. A cut position of the segment piece is selected such that two straight lines at two lateral sides of the segment shape is located within an area of a compressed portion of the processed friction material substrate. That is, a stepped or sunken compressed portion is provided on both sides of the segment piece.

Abstract: A clock recovery circuit includes a phase discriminating circuit for discriminating, at every edge of a received data signal, phase lead or phase lag of an identically directed edge of the clock signal, and outputting the phase discrimination signal; an edge detecting circuit for detecting edges of the received data signal, outputting an edge detection signal of a fixed pulse width, delaying the received data signal up to half of the fixed pulse width and outputting the delayed signal; an exclusive-OR gate for outputting, as an edge injection signal, an exclusive-OR signal between the phase discrimination signal and delayed signal; and a voltage-controlled oscillator for variably controlling frequency of ring oscillation by a frequency control voltage, injecting the edge injection signal into the loop of ring oscillation in a period of the fixed pulse width, and outputting a clock signal locked to the received data signal.