Abstract: The present invention provides a compound represented by the formula (I): (wherein R1 is a lower alkyl substituted by a lower alkoxy or a heterocyclic group, or a heterocyclic group; R2 is a lower alkyl optionally substituted by a phenyl; and R3 is a lower alkyl optionally substituted by a halogen, a lower alkoxy or a phenyl, or a fused polycyclic hydrocarbon group), which is well absorbed orally, exhibits durability of good blood level and has potent calpain inhibitory activity.

Abstract: A simulated moving bed apparatus and methods are described for continuously separating a target molecule from a liquid mixture, using a simulated moving bed system. The simulated moving bed system includes a plurality of filter cartridge modules in serial fluid communication. Each filter cartridge module includes a volume of stationary phase particulates adjacent a porous substrate layer. Each filter cartridge module also includes recirculation piping in fluid connection with a filter cartridge outlet and a filter cartridge inlet.

Abstract: Disclosed is a reference voltage generating circuit which includes resistors R0, R0 and R3, a differential amplifier A1 and transistors Q1, Q2 and Q3. The collectors of the transistors Q1 and Q2 are connected to differential input terminals of the differential amplifier, while one ends of the R0, R0 and R3 are connected in common to an output of the differential amplifier A1. The other ends of the two resistors R0 are connected in common to the collectors of the transistors Q1 and Q2, while the other end of the resistor R1 is connected to the collector and the base of the transistor Q3, which transistor Q3 has the base connected to the bases of the transistors Q1 and Q2. The emitter size ratio of the transistors Q1 and Q2 is set to 1:N. A current of a value approximately equal to that of the collector current of the transistor Q1 or Q2 and a current with a positive temperature coefficient larger than the first-stated current are caused to flow through the resistor R1.

Abstract: A composition containing a swelling agent is provided, which less burdens the stomach and intestine even after excessive intake. A food, anti-obesity agent and constipation alleviator each containing the composition is also provided. [Means for Solution] A composition comprises a swelling agent composed of a water-soluble polysaccharide swellable in Japanese Pharmacopoeia first fluid or Japanese Pharmacopoeia second fluid and water; and a swell inhibitor operative to control the swell of the swelling agent. The swelling agent and the swell inhibitor are mixed in the state of solution, unified and then dried.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: A single pass simulated moving bed apparatus and methods are described for continuously separating a target molecule from a liquid mixture, using a simulated moving bed system. The simulated moving bed system includes a plurality of filter cartridge modules in serial fluid communication. Each filter cartridge module includes a volume of stationary phase particulates adjacent a porous substrate layer. The volume of stationary phase particulates has a bed height of less than 1 centimeter.

Abstract: The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.

Abstract: A single pass simulated moving bed apparatus and methods are described for continuously separating a target molecule from a liquid mixture, using a simulated moving bed system. The simulated moving bed system includes a plurality of filter cartridge modules in serial fluid communication. Each filter cartridge module includes a volume of stationary phase particulates adjacent a porous substrate layer. The volume of stationary phase particulates has a bed height of less than 1 centimeter.

Abstract: A trigger-type liquid sprayer of the present invention is provided with a liquid sprayer body 2 having a nozzle 21 and a trigger lever 22 and a shroud 3 covering the liquid sprayer body 2 and sprays a liquid from a spray hole 211 in the nozzle 21 by a pulling operation of the trigger lever 22. The nozzle 21 is rotatable with respect to the liquid sprayer body 2 and provided so as to open/close a flow passage for the liquid according to a rotational position of the nozzle 21 when an operation lever 24 mounted on the nozzle 21 is rotationally moved, and an abutment portion 31 for positioning the nozzle 21 at a position where the flow passage is opened through abutment of the operation lever 24 is provided at the shroud 3.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

Abstract: A semiconductor device is configured to prevent misprogramming of fuse circuits therein. The semiconductor device includes the following elements. A group of fuse element circuits 911 is configured to store a first data defining the circuit configuration. A fuse element circuit 913 is configured to store a second data representing inhibition of programming the group of fuse element circuits. A control logic circuit 140 is configured to program the first and the second data on the fuse element circuits. An AND gate circuit 914 is configured to inhibit the control logic circuit 140 from programming the group of fuse element circuits 911 on condition that the fuse element circuit 913 has been programmed.

Abstract: A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the polysilicon film is embedded in a trench formed in a silicon substrate in order to elongate the effective channel length of the memory cell transistor. The other part of the polysilicon film is located above the trench, and an upper surface thereof is located above a surface of the silicon substrate (p-type well). Therefore, distances between the W film and a source and drain (n-type semiconductor regions) are ensured.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: A Web page having display elements such as a headline, a story body, subheads, and links to articles is obtained and rendered internally to obtain a position of each display element based on draw data. Each display element is classified into several clusters according to its position. Next, clusters having the same character attributes are classified as a group. A group having a high average of the number of characters within each of its clusters is determined as the story body and a group having a low average is determined as the headline. Then, individual pages including the story body and a top page including the headline, the subheads, and links to the story body pages are created. Therefore, the Web page is reconstructed as Web pages suitable for browsing in low-resolution display environments.

Abstract: A medical chair has a cranium position regulating device and a pelvis-and-knee position regulating device for respectively regulating the positions of the cranium and pelvis of a subject who sits on a seat. The cranium position regulating device and the pelvis-and-knee position regulating device have structures in which they butt against both right and left sides of the cranium and the pelvis, respectively, to cause both planes centered in a right-and-left direction of the cranium and the pelvis to be in a same central plane which extends in the direction of gravity. An ideal condition of the body of the subject in which vertical and horizontal balances are achieved against the force of gravity can be achieved to ensure physiological curvature of vertebrae and the condition can be maintained.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.