Patents by Inventor Masayuki Nakamura
Masayuki Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140102908Abstract: Disclosed is a resin-metal bonded body of an aluminum metal member and a thermoplastic resin member, which has improved bonding strength and good durability. Also disclosed is a method for producing such a resin-metal bonded body. Specifically disclosed is a resin-metal bonded body which is obtained by bonding an aluminum metal member with a thermoplastic resin member. In this resin-metal bonded body, the aluminum metal member and the thermoplastic resin member are bonded together by an anodic oxide coating having a film thickness of 70-1500 nm or an anodic oxide coating having a triazine thiol in the inner and upper portions. The anodic oxide coating has an infrared absorption spectrum peak intensity ascribed to OH group at 0.0001-0.16.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Applicant: TOADENKA CORPORATIONInventors: Masumi KUROYAMA, Tomonori ISHIKAWA, Kazuo KATO, Yaeko SASAKI, Shuhei MIURA, Masayuki NAKAMURA, Setsuko SATO
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Patent number: 8684235Abstract: A trigger-type liquid sprayer of the present invention is provided with a liquid sprayer body 2 having a nozzle 21 and a trigger lever 22 and a shroud 3 covering the liquid sprayer body 2 and sprays a liquid from a spray hole 211 in the nozzle 21 by a pulling operation of the trigger lever 22. The nozzle 21 is rotatable with respect to the liquid sprayer body 2 and provided so as to open/close a flow passage for the liquid according to a rotational position of the nozzle 21 when an operation lever 24 mounted on the nozzle 21 is rotationally moved, and an abutment portion 31 for positioning the nozzle 21 at a position where the flow passage is opened through abutment of the operation lever 24 is provided at the shroud 3.Type: GrantFiled: February 6, 2008Date of Patent: April 1, 2014Assignees: Kao Corporation, Yoshino Kogyosho Co., Ltd.Inventors: Shinichi Inaba, Takeshi Omi, Tetsuya Kobayashi, Takayuki Abe, Masayuki Nakamura, Hidesato Kizaki
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Publication number: 20140045666Abstract: Provided is a bag making apparatus with a simple configuration that: prevents fluctuations in tension, slippage of seal positions, and meandering or skewing of a web of film; allows the setting of precise initial conditions; reduces or makes unnecessary monitoring, and time and structures for adjustment; allows increased feed rate; and improves production efficiency. The bag making apparatus for packaging containers comprises: a tension control unit for controlling the continuous feed rate according to the values detected by a tension sensor of a tension detection roll; an optical detection unit for simultaneously recognizing multiple marks provided on the surface of the web of film at the respective positions thereof; a skewing correction unit; and a seal position correction unit for adjusting the positions of multiple sealing units in the feed direction.Type: ApplicationFiled: April 4, 2012Publication date: February 13, 2014Applicant: TOYO SEIKAN GROUP HOLDINGS, LTD.Inventors: Tadashi Endou, Masayuki Nakamura, Hironaga Shimizu, Hideki Yuge, Yuusuke Kuboki
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Publication number: 20140005185Abstract: The present invention provides an imidazooxazine compound represented by Formula (I) or a salt thereof, wherein A, B, C, and D are as defined in the specification.Type: ApplicationFiled: April 5, 2012Publication date: January 2, 2014Applicant: TAIHO PHARMACEUTICAL CO., LTD.Inventors: Masayuki Nakamura, Kenji Niiyama, Kaori Kamijo, Mitsuru Ohkubo, Toshiyasu Shimomura
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Patent number: 8605100Abstract: A drawing device includes a distinguish unit for distinguishing figure description information in scene data of each figure in a display screen, for tiles included in the display screen; an aggregation unit for aggregating a data size of the figure description information corresponding to the tiles; an address determination unit for determining a leading address in a memory area for storing the figure description information corresponding to each of the tiles, based on an aggregation result of each tile; and a memory write unit for sequentially writing, in the memory area, the figure description information distinguished as corresponding to the tiles, starting from the leading address determined for each corresponding tile, wherein the address determination unit determines the leading addresses so that the memory areas for storing the figure description information corresponding to the tiles are arranged in a physical address space in an order of drawing the tiles.Type: GrantFiled: November 21, 2012Date of Patent: December 10, 2013Assignees: Fujitsu Limited, Fujitsu Semiconductor LimitedInventors: Yasushi Sugama, Masayuki Nakamura
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Patent number: 8462167Abstract: A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.Type: GrantFiled: October 29, 2009Date of Patent: June 11, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Akihiro Kawahara, Makoto Adachi, Kouji Nishikawa, Masayuki Nakamura, Motonobu Mamiya, Kae Yamashita
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Patent number: 8422263Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.Type: GrantFiled: June 3, 2010Date of Patent: April 16, 2013Assignee: Elpida Memory, Inc.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Fumiyuki Osanai, Masayuki Nakamura, Hiroki Fujisawa
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Publication number: 20130084614Abstract: A method of removing a fermentation inhibitor from an aqueous mixture of hydrolysis products from cellulosic biomass is disclosed. The method includes providing an aqueous mixture of hydrolysis products from cellulosic biomass, the hydrolysis products comprising at least one of pentose or hexose sugars and a fermentation inhibitor that inhibits a microorganism otherwise capable of fermenting pentose or hexose sugars; and at least partially extracting the fermentation inhibitor from the aqueous mixture with a first extractant by a first liquid-liquid extraction through a first porous membrane to provide a first extract and a raffmate, the first extractant having a water solubility of less than one percent by weight. In some embodiments, the aqueous mixture contains an insufficient amount of the microorganism to ferment the aqueous mixture. In some embodiments, the aqueous mixture is a fermentation broth. A membrane solvent extraction system for carrying out the method is also disclosed.Type: ApplicationFiled: June 14, 2011Publication date: April 4, 2013Applicant: 3M INNOVATIVE PROPERTIES COMPANYInventors: Dan L. Fanselow, Masayuki Nakamura, Richard B. Ross, Brady P. Haislet, Alicia A. Petryk
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Patent number: 8394503Abstract: Disclosed is a resin-metal bonded article which is improved in adhesion between a copper component and a PPS or PBT resin. Also disclosed is a method for producing such a resin-metal bonded article. The resin-metal bonded article is obtained by bonding the resin component onto the surface of the copper component through a copper component bonding surface where there is copper oxide in the following range: 10%?Cu2O/(Cu2O+CuO)?75%. Preferably, this resin-metal bonded article further contains a triazine thiol derivative in the resin-component-side bonding surface of the copper component.Type: GrantFiled: December 15, 2008Date of Patent: March 12, 2013Assignee: Toadenka CorporationInventors: Masumi Kuroyama, Kazuo Kato, Tomonori Ishikawa, Yaeko Sasaki, Setsuko Sato, Masayuki Nakamura, Shuhei Miura
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Publication number: 20130037131Abstract: A control valve includes a signal pressure passage that transmits a pilot pressure of first and second pilot chambers as a signal pressure of another device, a connecting groove that is formed in a spool and connects the first pilot chamber to the signal pressure passage when the spool is in a neutral position, a connecting hole that is formed in the spool and connects the second pilot chamber to the signal pressure passage, and a check valve that is interposed in the connecting hole and permits a flow only from the second pilot chamber to the signal pressure passage. The connecting groove connects the first pilot chamber to the signal pressure passage when the pilot pressure is led into the first pilot chamber, and blocks communication between the first pilot chamber and the signal pressure passage when the pilot pressure is led into the second pilot chamber.Type: ApplicationFiled: January 27, 2012Publication date: February 14, 2013Applicant: KAYABA INDUSTRY CO., LTD.Inventors: Takeshi Fujiwara, Masayuki Nakamura
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Publication number: 20120250264Abstract: Disclosed herein is a memory module that includes a register buffer and a memory chip each mounted on a module substrate. Each of the command address output terminals belonging to the first group provided on the register buffer is connected to an associated one of the command address input terminals belonging to the first group provided on the memory chip through associated ones of the plurality of contact plugs and the first wiring layer. Each of the command address output terminals belonging to the second group provided on the register buffer is connected to an associated one of the command address input terminals belonging to the second group provided on the memory chip through associated ones of the plurality of contact plugs and the second wiring layer.Type: ApplicationFiled: March 27, 2012Publication date: October 4, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Fumiyuki OSANAI, Toshio SUGANO, Masayuki NAKAMURA
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Publication number: 20120214041Abstract: An electricity storage module includes: an electric storage unit block that is constituted by arraying a plurality of prismatic electric storage units through a holding member; and a cooling channel that is formed between the electric storage unit and the holding member, through which a cooling medium for cooling the electric storage unit flows. A part of a cooling medium inlet opening of the cooling channel is covered so that a flow speed of a cooling medium after flowing into the cooling channel is higher than a flow speed of a cooling medium before flowing into the cooling channel.Type: ApplicationFiled: August 12, 2010Publication date: August 23, 2012Applicants: HITACHI VEHICLE ENERGY, LTD., HITACHI, LTD.Inventors: Susumu Harada, Masayuki Nakamura, Kenji Kubo, Ryuji Kohno
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Patent number: 8247977Abstract: The plasma generator of our invention comprises of the induction coil which is symmetric with respect to the reference plane between two terminal ends. Plasma processing gas is supplied to a predetermined space, and high frequency electricity is supplied to the induction coil, thereby the plasma generator generates plasma in the space. The reference plane passes between the two terminal ends and through longitude axis of the induction coil. The plasma generator can generate plasma with high quality of homogeneous.Type: GrantFiled: July 24, 2009Date of Patent: August 21, 2012Assignee: Lam Research CorporationInventors: Georgy K. Vinogradov, Vladimir M. Menagarishvili, Tetsuhiko Shimamura, Masayuki Nakamura
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Publication number: 20120074018Abstract: To provide an embossing device, an embossing method and an embossed can which are capable of conducting embossing having a non-shaped section and an arbitral number of embossed areas, and are capable of improving quality or productivity. An embossed can 10 is a double-embossed surface can in which on a can barrel 101 a first pattern 104 is printed; a first concave part 105 is formed in the state that it is so positioned as to almost conform to the first pattern 104; a second pattern 106 is printed at a position which is distant in the circumferential direction with the non-shaped section therebetween; and a second concave portion 107 is formed in the state that it is so positioned as to almost conform to the second pattern 106.Type: ApplicationFiled: May 28, 2010Publication date: March 29, 2012Applicant: TOYO SEIKAN KAISHA, LTD.Inventors: Kazumoto Obata, Keiji Sasaki, Wataru Ookubo, Masayuki Nakamura
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Patent number: 8138197Abstract: The invention relates to a compound of a general formula (I): wherein Ar1 represents a group formed from an aromatic ring selected from a group consisting of benzene, pyrazole, isoxazole, pyridine, indole, 1H-indazole, 1H-furo[2,3-c]pyrazole, 1H-thieno[2,3-c]pyrazole, benzimidazole, 1,2-benzisoxazole, imidazo[1,2-a]pyridine, imidazo[1,5-a]pyridine and 1H-pyrazolo[3,4-a]pyridine, having Ar2, and optionally having one or two or more substituents selected from R3; R1 and R2 each independently represent a hydrogen atom, a halogen atom, a cyano group, a C2-C6 alkenyl group, a C1-C6 alkoxy group, a C2-C7 alkanoyl group, a C2-C7 alkoxycarbonyl group, an aralkyloxycarbonyl group, a carbamoyl-C1-C6 alkoxy group, a carboxy-C2-C6 alkenyl group, or a group of -Q1-N(Ra)-Q2-Rb; or a C1-C6 alkyl group optionally having a substituent; or an aryl or heterocyclic group optionally having a substituent; or a C1-C6 alkyl group or a C2-C6 alkenyl group having the aryl or heterocyclic group; T and U each independently represent a nType: GrantFiled: January 8, 2008Date of Patent: March 20, 2012Assignees: MSD K.K., Merck Sharp & Dohme Corp.Inventors: Tomoharu Iino, Hideki Jona, Hideki Kurihara, Masayuki Nakamura, Kenji Niiyama, Jun Shibata, Tadashi Shimamura, Hitomi Watanabe, Takeru Yamakawa, Lihu Yang
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Publication number: 20120040234Abstract: A laminated battery formed by laminating a plurality of flat cells each having an electrode tab includes: an insulating member disposed to prevent a short-circuit in the electrode tab; and a terminal connected to the electrode tab, wherein a tip end side of the terminal is supported by a support member provided on the insulating member.Type: ApplicationFiled: May 14, 2010Publication date: February 16, 2012Inventors: Ryuichi Amagai, Masayuki Nakamura
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Patent number: 8004332Abstract: There are provided a duty ratio control apparatus for altering a duty ratio of a clock signal to output an altered clock signal, including a first variable delay section that outputs a first delayed clock signal generated by delaying the clock signal by a predetermined first delay time, and a phase comparing section that compares, in terms of phase, an edge of the clock signal and an edge of the first delayed clock signal and generates the altered clock signal having a pulse width determined by a phase difference obtained by the comparison, and a duty ratio control method.Type: GrantFiled: November 3, 2009Date of Patent: August 23, 2011Assignee: Advantest CorporationInventor: Masayuki Nakamura
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Publication number: 20110102038Abstract: There are provided a duty ratio control apparatus for altering a duty ratio of a clock signal to output an altered clock signal, including a first variable delay section that outputs a first delayed clock signal generated by delaying the clock signal by a predetermined first delay time, and a phase comparing section that compares, in terms of phase, an edge of the clock signal and an edge of the first delayed clock signal and generates the altered clock signal having a pulse width determined by a phase difference obtained by the comparison, and a duty ratio control method.Type: ApplicationFiled: November 3, 2009Publication date: May 5, 2011Applicant: ADVANTEST CORPORATIONInventor: Masayuki NAKAMURA
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Publication number: 20110033711Abstract: Disclosed is a resin-metal bonded article which is improved in adhesion between a copper component and a PPS or PBT resin. Also disclosed is a method for producing such a resin-metal bonded article. The resin-metal bonded article is obtained by bonding the resin component onto the surface of the copper component through a copper component bonding surface where there is copper oxide in the following range: 10%?Cu2O/(Cu2O+CuO)?75%. Preferably, this resin-metal bonded article further contains a triazine thiol derivative in the resin-component-side bonding surface of the copper component.Type: ApplicationFiled: December 15, 2008Publication date: February 10, 2011Applicants: Denso Corporation, Toadenka CorporationInventors: Masumi Kuroyama, Kazuo Kato, Tomonori Ishikawa, Yaeko Sasaki, Setsuko Sato, Masayuki Nakamura, Shuhei Miura
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Patent number: RE42659Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.Type: GrantFiled: June 7, 2007Date of Patent: August 30, 2011Inventors: Tsugio Takahashi, Goro Kitsukawa, Takesada Akiba, Yasushi Kawase, Masayuki Nakamura