Abstract: An isolation insulating film is formed so that an active region of a first access transistor and a substrate contact region can be integrated with each other in a plan view. A dummy gate electrode is formed on the semiconductor substrate between the active region of the first access transistor and the substrate contact region. The dummy gate electrode is electrically connected to a P-type impurity region of the substrate contact region.

Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.

Abstract: A memory module includes a plurality of data connectors provided along a long side of a module substrate, a plurality of memory chips and a plurality of data register buffers mounted on the module substrate, a data line that connects the data connectors and the data register buffers, and data lines that connect the data register buffers and the memory chips. Each of the data register buffers and a plurality of data connectors and a plurality of memory chips corresponding to the data register buffer are arranged side by side in a direction of a short side of the module substrate. According to the present invention, because each line length of the data lines is considerably shortened, it is possible to realize a considerably high data transfer rate.

Abstract: A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.

Abstract: A ZQ calibration command is internally generated from an external command different from a ZQ calibration command so as to automatically perform an additional ZQ calibration operation. A command interval between an inputted command and a next command is effectively employed to obtain a ZQ calibration period. The external command different from the ZQ calibration command is preferably a self-refreshed command. The addition of the ZQ calibration operation shortens intervals between ZQ calibration operations. Thus, it is possible to obtain a ZQ calibration circuit capable of performing a ZQ calibration operation more accurately.

Abstract: Disclosed is a resin-metal bonded body of an aluminum metal member and a thermoplastic resin member, which has improved bonding strength and good durability. Also disclosed is a method for producing such a resin-metal bonded body. Specifically disclosed is a resin-metal bonded body which is obtained by bonding an aluminum metal member with a thermoplastic resin member. In this resin-metal bonded body, the aluminum metal member and the thermoplastic resin member are bonded together by an anodic oxide coating having a film thickness of 70-1500 nm or an anodic oxide coating having a triazine thiol in the inner and upper portions. The anodic oxide coating has an infrared absorption spectrum peak intensity ascribed to OH group at 0.0001-0.16.

Abstract: A semiconductor device is configured to prevent misprogramming of fuse circuits therein. The semiconductor device includes the following elements. A group of fuse element circuits 911 is configured to store a first data defining the circuit configuration. A fuse element circuit 913 is configured to store a second data representing inhibition of programming the group of fuse element circuits. A control logic circuit 140 is configured to program the first and the second data on the fuse element circuits. An AND gate circuit 914 is configured to inhibit the control logic circuit 140 from programming the group of fuse element circuits 911 on condition that the fuse element circuit 913 has been programmed.

Abstract: There is provided an oscillator including: a reference signal generator that generates a reference signal having a reference frequency; a phase comparator that outputs a voltage in accordance with a phase difference between the reference signal and a feedback signal; a loop filter that receives a voltage output from the phase comparator, and gain-adjusts a voltage output from the phase comparator by means of an external control signal; a voltage controlled oscillator that oscillates an output signal at a frequency in accordance with an adjusted signal having been gain-adjusted by the loop filter; and a frequency divider that feeds back a frequency-divided signal resulting from frequency-dividing the output signal, to the phase comparator as the feedback signal.

Abstract: A reference voltage generating circuit includes a current generating section, a voltage generating section, a voltage dividing circuit, and a synthesis section. The current generating section generates a first current having a positive temperature coefficient. The voltage generating section generates a voltage having a negative temperature coefficient. The voltage dividing circuit divides the voltage of the negative temperature coefficient, generated by the voltage generating section. The synthesis section generates a voltage which is the sum of a terminal voltage obtained on causing the first current through a resistor and a voltage obtained on dividing the voltage having the negative temperature coefficient by the voltage dividing circuit, and outputs the sum voltage generated as a reference voltage.

Abstract: A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: A line plotting method for plotting lines whose coordinates are given on a display screen on which pixels are arranged according to a prescribed rule, the method includes correcting coordinates at the end point of a line on the basis of which the end point is a starting point or an ending point or whether the end point is inside a prescribed frame determining whether a direction from a starting point of a line after correction toward its ending point horizontally or vertically is the same as a direction from a starting point before correction of a line toward its ending point determining whether integer values of the coordinates of starting and ending points after correction are the same when directions from starting points after and before correction of a line toward their ending points are not matched.

Abstract: When connecting a semiconductor device such as an IC chip with a circuit board by the flip-chip method, a semiconductor device is provided without forming bumps thereon, which enables highly reliable and low cost connection between the IC chip and circuit board while ensuring suppressing short-circuiting, lowering connection costs, suppressing stress concentrations at the joints and reducing damage of the IC chip or circuit board. The bumpless semiconductor device is provided with electrode pads 2 on the surface thereof and with a passivation film 3 at the periphery of the electrode pads 2, and conductive particles 4 are metallically bonded to the electric pads 2. Composite particles in which a metallic plating layer is formed at the surface of resin particles are employed as the conductive particles 4.

Abstract: The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.

Abstract: There is provided an oscillator including: a reference signal generator that generates a reference signal having a reference frequency; a phase comparator that outputs a voltage in accordance with a phase difference between the reference signal and a feedback signal; a loop filter that receives a voltage output from the phase comparator, and gain-adjusts a voltage output from the phase comparator by means of an external control signal; a voltage controlled oscillator that oscillates an output signal at a frequency in accordance with an adjusted signal having been gain-adjusted by the loop filter; and a frequency divider that feeds back a frequency-divided signal resulting from frequency-dividing the output signal, to the phase comparator as the feedback signal.

Abstract: The plasma generator of our invention comprises of the induction coil which is symmetric with respect to the reference plane between two terminal ends. Plasma processing gas is supplied to a predetermined space, and high frequency electricity is supplied to the induction coil, thereby the plasma generator generates plasma in the space. The reference plane passes between the two terminal ends and through longitude axis of the induction coil. The plasma generator can generate plasma with high quality of homogeneous.

Abstract: The invention relates to a compound of a general formula (I): wherein Ar1 represents a group formed from an aromatic ring selected from a group consisting of benzene, pyrazole, isoxazole, pyridine, indole, 1H-indazole, 1H-furo[2,3-c]pyrazole, 1H-thieno[2,3-c]pyrazole, benzimidazole, 1,2-benzisoxazole, imidazo[1,2-a]pyridine, imidazo[1,5-a]pyridine and 1H-pyrazolo[3,4-b]pyridine, having Ar2, and optionally having one or two or more substituents selected from R3: R1 and R2 each independently represent a hydrogen atom, a halogen atom, a cyano group, a C2-C6 alkenyl group, a C1-C6 alkoxy group, a C2-C7 alkanoyl group, a C2-C7 alkoxycarbonyl group, an aralkyloxycarbonyl group, a carbamoyl-C1-C6 alkoxy group, a carboxy-C2-C6 alkenyl group, or a group of -Q1-N(Ra)-Q2-Rb; or a C1-C6 alkyl group optionally having a substituent; or an aryl or heterocyclic group optionally having a substituent; or a C1-C6 alkyl group or a C2-C6 alkenyl group having the aryl or heterocyclic group; T and U each independently represent a n

Abstract: In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

Abstract: A reference voltage generating circuit is described. The circuit includes a current generating section that generates a first current having a positive temperature coefficient, a voltage generating section that generates a voltage having a negative temperature coefficient, a synthesis section that generates a voltage which is the sum of a voltage having a positive temperature coefficient and developed across both terminals of a resistor, where the voltage has a negative temperature coefficient, and a compensation current generating section that generates a second current having a positive temperature coefficient. The current corresponding to the sum of said first and second currents is caused to flow through the resistor. The synthesis section generates a voltage which is a sum of a terminal voltage of the resistor by the sum current of the first and second currents and the voltage having a negative temperature coefficient.

Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.