Patents by Inventor Masazumi Amagai
Masazumi Amagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240014119Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.Type: ApplicationFiled: September 21, 2023Publication date: January 11, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Han KIM, Masazumi Amagai, Ju Ho Kim, Tae Sung Jeong
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Patent number: 11810848Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.Type: GrantFiled: August 13, 2021Date of Patent: November 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Han Kim, Masazumi Amagai, Ju Ho Kim, Tae Sung Jeong
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Publication number: 20210375739Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.Type: ApplicationFiled: August 13, 2021Publication date: December 2, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Han KIM, Masazumi AMAGAI, Ju Ho KIM, Tae Sung JEONG
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Patent number: 11094623Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.Type: GrantFiled: February 11, 2020Date of Patent: August 17, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Han Kim, Masazumi Amagai, Ju Ho Kim, Tae Sung Jeong
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Publication number: 20200176370Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.Type: ApplicationFiled: February 11, 2020Publication date: June 4, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Han Kim, Masazumi Amagai, Ju Ho Kim, Tae Sung Jeong
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Patent number: 10580728Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.Type: GrantFiled: March 13, 2017Date of Patent: March 3, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Han Kim, Masazumi Amagai, Ju Ho Kim, Tae Sung Jeong
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Publication number: 20170372995Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.Type: ApplicationFiled: March 13, 2017Publication date: December 28, 2017Inventors: Sung Han KIM, Masazumi AMAGAI, Ju Ho KIM, Tae Sung JEONG
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Patent number: 8598029Abstract: A semiconductor device, which comprises a workpiece with an outline and a plurality of contact pads and further an external part with a plurality of terminal pads. This part is spaced from the workpiece and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element interconnects each of the contact pads with its respective terminal pad. Thermoplastic material fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline substantially in line with the outline of the workpiece, and fills the space substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.Type: GrantFiled: May 8, 2012Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Masako Watanabe, Masazumi Amagai
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Patent number: 8304883Abstract: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.Type: GrantFiled: May 24, 2011Date of Patent: November 6, 2012Assignee: Texas Instruments IncorporatedInventors: Yoshimi Takahashi, Masazumi Amagai
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Publication number: 20120220080Abstract: A semiconductor device, which comprises a workpiece with an outline and a plurality of contact pads and further an external part with a plurality of terminal pads. This part is spaced from the workpiece and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element interconnects each of the contact pads with its respective terminal pad. Thermoplastic material fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline substantially in line with the outline of the workpiece, and fills the space substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.Type: ApplicationFiled: May 8, 2012Publication date: August 30, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Masako Watanabe, Masazumi Amagai
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Patent number: 8193085Abstract: A semiconductor device (1700), which comprises a workpiece (1201) with an outline (1711) and a plurality of contact pads (1205) and further an external part (1701) with a plurality of terminal pads (1702). This part is spaced from the workpiece, and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element (1203) interconnects each of the contact pads with its respective terminal pad. Thermoplastic material (1204) fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline (1711) substantially in line with the outline of the workpiece, and fills the space (1707) substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.Type: GrantFiled: February 10, 2010Date of Patent: June 5, 2012Assignee: Texas Instruments IncorporatedInventors: Masako Watanabe, Masazumi Amagai
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Patent number: 8097964Abstract: An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.Type: GrantFiled: December 29, 2009Date of Patent: January 17, 2012Assignee: Texas Instruments IncorporatedInventors: Jeffrey Alan West, Margaret Rose Simmons-Matthews, Masazumi Amagai
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Publication number: 20110254150Abstract: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.Type: ApplicationFiled: May 24, 2011Publication date: October 20, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yoshimi Takahashi, Masazumi Amagai
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Patent number: 7971351Abstract: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.Type: GrantFiled: March 9, 2009Date of Patent: July 5, 2011Assignee: Texas Instruments IncorporatedInventors: Yoshimi Takahashi, Masazumi Amagai
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Patent number: 7884009Abstract: A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.Type: GrantFiled: July 22, 2010Date of Patent: February 8, 2011Assignee: Texas Instruments IncorporatedInventor: Masazumi Amagai
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Publication number: 20110024899Abstract: Various embodiments provide semiconductor devices having cavity substrate structures for package-on-package assembly and methods for their fabrication. In one embodiment, the cavity substrate structure can include at least one top interconnect via formed within a top substrate. The top substrate can be disposed over a base substrate having at least one base interconnect via that is not aligned with the top interconnect via. Semiconductor dies can be assembled in an open cavity of the top substrate and attached to a base center portion of the base substrate of the cavity substrate structure. A top semiconductor package can be mounted over the top substrate of the cavity substrate structure.Type: ApplicationFiled: July 28, 2009Publication date: February 3, 2011Inventors: Kenji MASUMOTO, Masazumi Amagai, Masayuki Yoshino, Yukio Moriyama
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Publication number: 20100291734Abstract: A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.Type: ApplicationFiled: July 22, 2010Publication date: November 18, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Masazumi AMAGAI
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Patent number: 7786599Abstract: A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.Type: GrantFiled: October 19, 2009Date of Patent: August 31, 2010Assignee: Texas Instruments IncorporatedInventor: Masazumi Amagai
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Publication number: 20100171226Abstract: An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.Type: ApplicationFiled: December 29, 2009Publication date: July 8, 2010Applicant: TEXAS INSTRUMENTS, INC.Inventors: Jeffrey Alan West, Margaret Rose Simmons-Matthews, Masazumi Amagai
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Publication number: 20100144098Abstract: A semiconductor device (1700), which comprises a workpiece (1201) with an outline (1711) and a plurality of contact pads (1205) and further an external part (1701) with a plurality of terminal pads (1702). This part is spaced from the workpiece, and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element (1203) interconnects each of the contact pads with its respective terminal pad. Thermoplastic material (1204) fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline (1711) substantially in line with the outline of the workpiece, and fills the space (1707) substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.Type: ApplicationFiled: February 10, 2010Publication date: June 10, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Masako WATANABE, Masazumi AMAGAI