Patents by Inventor Masazumi Amagai
Masazumi Amagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7701071Abstract: A semiconductor device (1700), which comprises a workpiece (1201) with an outline (1711) and a plurality of contact pads (1205) and further an external part (1701) with a plurality of terminal pads (1702). This part is spaced from the workpiece, and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element (1203) interconnects each of the contact pads with its respective terminal pad. Thermoplastic material (1204) fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline (1711) substantially in line with the outline of the workpiece, and fills the space (1707) substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.Type: GrantFiled: March 24, 2005Date of Patent: April 20, 2010Assignee: Texas Instruments IncorporatedInventors: Masako Watanabe, Masazumi Amagai
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Publication number: 20100090323Abstract: The present invention provides a spacer sheet for a complex type semiconductor device provided between the semiconductor packages of a complex type semiconductor device formed by laminating plural semiconductor packages, comprising through holes of an array corresponding to electrodes which can be provided onto a substrate of one semiconductor package and which are formed in order to connect and wire one semiconductor package with the other semiconductor package and a space part corresponding to a principal part of the above one semiconductor package mounted on the substrate or a principal part of the other semiconductor package opposed to the substrate and a production process for a complex type semiconductor device in which the above spacer sheet is used.Type: ApplicationFiled: October 22, 2007Publication date: April 15, 2010Applicant: Lintec CorporationInventors: Tomonori Shinoda, Hironori Shizuhata, Hirofumi Shinoda, Yuji Kawamata, Takeshi Tashima, Masato Shimamura, Masako Watanabe, Masazumi Amagai
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Patent number: 7679002Abstract: In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is located within the mold region and on a solder joint side of the substrate core and has a second conductive metal density associated therewith, wherein the second conductive metal density within the mold region is about equal to or less than the first conductive metal density within the mold region.Type: GrantFiled: August 22, 2006Date of Patent: March 16, 2010Assignee: Texas Instruments IncorporatedInventors: Masazumi Amagai, Kenji Masumoto
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Publication number: 20100032840Abstract: A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.Type: ApplicationFiled: October 19, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Masazumi AMAGAI
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Publication number: 20100025837Abstract: The present invention relates to a complex type semiconductor device formed by laminating plural semiconductor packages, wherein it comprises: an upper semiconductor package which comprises a substrate for wiring and connecting provided with electrodes for conducting packages on a lower surface in the upper semiconductor package and a principal part of the upper semiconductor package disposed on an upper surface and/or a lower surface of the above substrate and which constitutes a relatively upper part, a lower semiconductor package which comprises a substrate for wiring and connecting provided with electrodes for conducting packages on an upper surface in the lower semiconductor package and a principal part of the lower semiconductor package disposed on an upper surface and/or a lower surface of the above substrate and which constitutes a relatively lower part, a spacer sheet which comprises a space part corresponding to the principal part of the upper semiconductor package and/or the principal part of thType: ApplicationFiled: October 22, 2007Publication date: February 4, 2010Applicant: LINTEC CORPORATIONInventors: Tomonori Shinoda, Hironori Shizuhata, Hirofumi Shinoda, Yuji Kawamata, Takeshi Tashima, Masato Shimamura, Masako Watanabe, Masazumi Amagai
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Patent number: 7626274Abstract: A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.Type: GrantFiled: February 3, 2006Date of Patent: December 1, 2009Assignee: Texas Instruments IncorporatedInventor: Masazumi Amagai
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Publication number: 20090176336Abstract: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.Type: ApplicationFiled: March 9, 2009Publication date: July 9, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yoshimi TAKAHASHI, Masazumi AMAGAI
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Patent number: 7520052Abstract: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.Type: GrantFiled: June 27, 2006Date of Patent: April 21, 2009Assignee: Texas Instruments IncorporatedInventors: Yoshimi Takahashi, Masazumi Amagai
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Publication number: 20080157353Abstract: A microelectronic device package interconnect for electrically connecting a plurality of substrates is provided. The microelectronic device package interconnect comprises an insulative layer positioned on a substrate, wherein the insulative layer has an opening extending through the insulative layer to the substrate. The microelectronic device package interconnect further comprises solder positioned in the opening.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Applicant: Texas Instruments IncorporatedInventors: Masako Watanabe, Masazumi Amagai
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Publication number: 20080048303Abstract: In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is located within the mold region and on a solder joint side of the substrate core and has a second conductive metal density associated therewith, wherein the second conductive metal density within the mold region is about equal to or less than the first conductive metal density within the mold region.Type: ApplicationFiled: August 22, 2006Publication date: February 28, 2008Applicant: Texas Instruments IncorporatedInventors: Masazumi Amagai, Kenji Masumoto
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Publication number: 20070243098Abstract: [Problem]Mobile electronic equipment is often dropped during use or transport, and the soldered joints of electronic parts sometimes peel off due to the impact when dropped. In addition, they undergo heat cycles in which internal coils, resistors, and the like generate heat and soldered joints increase in temperature during operation of electronic equipment and cool off during periods of non-use. With a conventional Sn—Ag base lead-free solder, the impact resistance and resistance to heat cycles of minute portions such as solder bumps were not adequate. The present invention provides a lead-free solder alloy, bumps of which have excellent impact resistance and resistance to heat cycles. Means for Solving the Problem The present invention is a lead-free solder alloy comprising 0.1—less than 2.0 mass % of Ag, 0.01-0.1 mass % of Cu, 0.005-0.1 mass % of Zn, and a remainder of Sn, to which Ga, Ge, or P may be added, and to which Ni or Co may be further added.Type: ApplicationFiled: July 29, 2004Publication date: October 18, 2007Inventors: Tsukasa Ohnishi, Tokuro Yamaki, Masazumi Amagai, Masako Watanabe
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Patent number: 7282175Abstract: A lead-free solder includes 0.05-5 mass % of Ag, 0.01-0.5 mass % of Cu, at least one of P, Ge, Ga, Al, and Si in a total amount of 0.001-0.05 mass %, and a remainder of Sn. One or more of a transition element for improving resistance to heat cycles, a melting point lowering element such as Bi, In, or Zn, and an element for improving impact resistance such as Sb may be added.Type: GrantFiled: April 15, 2004Date of Patent: October 16, 2007Assignee: Senju Metal Industry Co., Ltd.Inventors: Masazumi Amagai, Masako Watanabe, Kensho Murata, Yoshitaka Toyoda, Minoru Ueshima, Tsukasa Ohnishi, Takeshi Tashima, Daisuke Souma, Takahiro Roppongi, Hiroshi Okada
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Publication number: 20070182006Abstract: A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.Type: ApplicationFiled: February 3, 2006Publication date: August 9, 2007Inventor: Masazumi Amagai
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Publication number: 20070170599Abstract: A tape for use as a carrier in semiconductor assembly, which has one or more base sheets 101 of polymeric, preferably thermoplastic, material having first (101a) and second (101b) surfaces. A polymeric adhesive film (102, 104) and a foil (103, 105) of different, preferably inert, material are attached to the base sheet on both the first and second surface sides; they thus provide a thickness (120) to the tape. A plurality of holes is formed through the thickness of the tape; the holes are preferably tapered with an angle between about 70° and 80° with the second tape surface. A reflow metal element (301), with a preferred diameter (302) about equal to the tape thickness, is held in each of the holes.Type: ApplicationFiled: January 24, 2006Publication date: July 26, 2007Inventors: Masazumi Amagai, Masako Watanabe
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Publication number: 20060292753Abstract: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.Type: ApplicationFiled: June 27, 2006Publication date: December 28, 2006Inventors: Yoshimi Takahashi, Masazumi Amagai
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Publication number: 20060214314Abstract: A semiconductor device (1700), which comprises a workpiece (1201) with an outline (1711) and a plurality of contact pads (1205) and further an external part (1701) with a plurality of terminal pads (1702). This part is spaced from the workpiece, and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element (1203) interconnects each of the contact pads with its respective terminal pad. Thermoplastic material (1204) fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline (1711) substantially in line with the outline of the workpiece, and fills the space (1707) substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.Type: ApplicationFiled: March 24, 2005Publication date: September 28, 2006Inventors: Masako Watanabe, Masazumi Amagai
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Patent number: 7042070Abstract: A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.Type: GrantFiled: July 2, 2003Date of Patent: May 9, 2006Assignee: Texas Instruments IncorporatedInventors: Chee Kiang Yew, Masazumi Amagai
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Patent number: 7029542Abstract: A lead-free solder alloy comprises 1.0–5.0 wt % Ag, 0.01–0.5 wt % Ni, one or both of (a) 0.001–0.05 wt % Co and (b) at least one of P, Ge, and Ga in a total amount of 0.001–0.05 wt %, and a remainder of Sn. The solder can form solder bumps which have a high bonding strength and which do not undergo yellowing after soldering.Type: GrantFiled: July 8, 2003Date of Patent: April 18, 2006Assignee: Senju Metal Industry Co., Ltd.Inventors: Masazumi Amagai, Masako Watanabe, Kensho Murata, Osamu Munekata, Yoshitaka Toyoda, Minoru Ueshima, Tsukasa Ohnishi, Hiroshi Okada
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Publication number: 20050127498Abstract: A semiconductor device comprising a semiconductor chip having an active and a passive surface, the passive surface adhesively attached to a substrate film by means of a multilayer composite; this composite comprising a metal foil having first and second surfaces and an adhesive layer attached on each of these surfaces. The multilayer composite has an average modulus larger than the modulus of the encapsulating molding compound used in the semiconductor device. By applying the composite to assembling face-up chip-scale devices, stress in solder joints is reduced and solder fatigue life enhanced.Type: ApplicationFiled: February 3, 2005Publication date: June 16, 2005Inventors: Masazumi Amagai, Akira Karashima
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Patent number: 6873059Abstract: A semiconductor device comprising a semiconductor chip having an active and a passive surface, the passive surface adhesively attached to a substrate film by means of a multilayer composite; this composite comprising a metal foil having first and second surfaces and an adhesive layer attached on each of these surfaces. The multilayer composite has an average modulus larger than the modulus of the encapsulating molding compound used in the semiconductor device. By applying the composite to assembling face-up chip-scale devices, stress in solder joints is reduced and solder fatigue life enhanced.Type: GrantFiled: November 13, 2001Date of Patent: March 29, 2005Assignee: Texas Instruments IncorporatedInventors: Masazumi Amagai, Akira Karashima