Patents by Inventor Masood Murtuza
Masood Murtuza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8039309Abstract: A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness, and then electrically coupling semiconductor dies to the formed patterns on the conductive plate. The method further includes encapsulating at least a portion of the dies and the conductive plate with an encapsulant and removing a portion of the conductive plate from the side opposite the patterned side to form conductive traces based on the formed pattern.Type: GrantFiled: May 7, 2008Date of Patent: October 18, 2011Assignee: Texas Instruments IncorporatedInventors: Masood Murtuza, Satyendra Singh Chauhan, Donald C. Abbott
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Patent number: 8017439Abstract: A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article.Type: GrantFiled: January 26, 2010Date of Patent: September 13, 2011Assignee: Texas Instruments IncorporatedInventors: Yoshimi Takahashi, Masood Murtuza, Rajiv Dunne, Satyendra Singh Chauhan
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Publication number: 20110183464Abstract: A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article.Type: ApplicationFiled: January 26, 2010Publication date: July 28, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yoshimi Takahashi, Masood Murtuza, Rajiv Dunne, Satyendra Singh Chauhan
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Patent number: 7915080Abstract: A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and TSV precursors including embedded TSV tips to form a die-wafer stack. The die-wafer stack is thinned beginning from the bottom surface of the TSV wafer to form a thinned die-wafer stack. The thinning includes exposing the embedded TSV tips to provide electrical access thereto from the bottom surface of the TSV wafer. The thinned die-wafer stack can be singulated to form a plurality of thinned die stacks.Type: GrantFiled: October 8, 2009Date of Patent: March 29, 2011Assignee: Texas Instruments IncorporatedInventors: Yoshimi Takahashi, Masood Murtuza, Rajiv Dunne, Satyendra Chauhan
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Patent number: 7883936Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).Type: GrantFiled: November 16, 2009Date of Patent: February 8, 2011Assignee: Texas Instruments IncorporatedInventors: Prema Palaniappan, Masood Murtuza, Satyendra S Chauhan
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Patent number: 7790597Abstract: A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adhere the conductive powder to the end of the bump. The powder can be flowed, for example by heating, to distribute it across the end of the bump. The flowed powder can be placed in contact with a conductive pad of a receiving substrate and can then be reflowed to facilitate electrical connection between the bump and the conductive pad.Type: GrantFiled: June 6, 2008Date of Patent: September 7, 2010Assignee: Texas Instruments IncorporatedInventors: Satyendra S. Chauhan, Rajiv C. Dunne, Gary P. Morrison, Masood Murtuza
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Publication number: 20100159643Abstract: A method for bonding IC die to TSV wafers includes bonding at least one singulated IC die to respective ones of a plurality of IC die on a TSV wafer that includes a top semiconductor surface and TSV precursors including embedded TSV tips to form a die-wafer stack. The die-wafer stack is thinned beginning from the bottom surface of the TSV wafer to form a thinned die-wafer stack. The thinning includes exposing the embedded TSV tips to provide electrical access thereto from the bottom surface of the TSV wafer. The thinned die-wafer stack can be singulated to form a plurality of thinned die stacks.Type: ApplicationFiled: October 8, 2009Publication date: June 24, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: YOSHIMI TAKAHASHI, MASOOD MURTUZA, RAJIV DUNNE, SATYENDRA CHAUHAN
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Publication number: 20100062567Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).Type: ApplicationFiled: November 16, 2009Publication date: March 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Prema PALANIAPPAN, Masood MURTUZA, Satyendra Singh CHAUHAN
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Patent number: 7642649Abstract: A semiconductor device employs a support structure to mitigate damage to dielectric layers having a low dielectric constant (k). The semiconductor device includes at least one inter-level dielectric layer (ILD) comprising a material having a low dielectric constant (k), and at least one support structure disposed within the low-k dielectric layer. The support structure mitigates damage of the semiconductor device by providing a mechanically stable interface between two layers in the semiconductor device.Type: GrantFiled: December 1, 2003Date of Patent: January 5, 2010Assignee: Texas Instruments IncorporatedInventor: Masood Murtuza
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Patent number: 7635914Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).Type: GrantFiled: May 17, 2007Date of Patent: December 22, 2009Assignee: Texas Instruments IncorporatedInventors: Prema Palaniappan, Masood Murtuza, Satyendra Singh Chauhan
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Publication number: 20090297879Abstract: A solder joint (200) has a first contact pad 114 and a second contact pad 124 of a first metal, preferably copper, facing each other across a gap. A coat and 125, respectively) of a second metal, preferably nickel, covers each pad. A layer 201 of crystals of first intermetallic compounds, such as Ni3Sn4 and (Ni, Cu)3Sn4, covers the surface of each coat. Isolated crystals 202 of second intermetallic compounds, such as Cu6Sn5 and (Cu, Ni)6Sn5, different from the first intermetallic compounds, are dispersed on top of the layer 201 of crystals of the first intermetallic compounds. A solder alloy 203 including a third metal, preferably tin, and the first metal fills the gap. The solder alloy 203 may further include a fourth metal, preferably selected from a group of metals including silver, zinc, and indium.Type: ApplicationFiled: May 11, 2009Publication date: December 3, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kejun ZENG, Rajiv DUNNE, Masood MURTUZA
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Publication number: 20090278245Abstract: A packaged electronic device includes a leadframe including a die pad, a first, second, and third lead pin surrounding the die pad. An IC die is assembled in a face-up configuration on the lead frame. The IC die includes a substrate having an active top surface and a bottom surface, wherein the top surface includes integrated circuitry including an input pad, an output pad, a power supply pad, and a ground pad, and a plurality of through-substrate vias (TSVs) including an electrically conductive filler material and a dielectric liner. The TSVs couple the input pad to the first lead pin, the output pad to the second lead pin, the power supply pad to a third lead pin or a portion of the die pad. A fourth TSV couples pads coupled to the ground node to the die pad or a portion of the die pad for a split die pad.Type: ApplicationFiled: May 8, 2009Publication date: November 12, 2009Applicant: TEXAS INSTRUMENTS INCInventors: THOMAS D. BONIFIELD, GARY P. MORRISON, RAJIV DUNNE, SATYENDRA S. CHAUHAN, MASOOD MURTUZA
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Publication number: 20090278244Abstract: A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 ?m. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame.Type: ApplicationFiled: May 8, 2009Publication date: November 12, 2009Applicant: TEXAS INSTRUMENTS INCInventors: RAJIV DUNNE, GARY P. MORRISON, SATYENDRA S. CHAUHAN, MASOOD MURTUZA, THOMAS D. BONIFIELD
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Publication number: 20090014898Abstract: A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adhere the conductive powder to the end of the bump. The powder can be flowed, for example by heating, to distribute it across the end of the bump. The flowed powder can be placed in contact with a conductive pad of a receiving substrate and can then be reflowed to facilitate electrical connection between the bump and the conductive pad.Type: ApplicationFiled: June 6, 2008Publication date: January 15, 2009Inventors: Satyendra S. Chauhan, Rajiv C. Dunne, Gary P. Morrison, Masood Murtuza
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Publication number: 20080283992Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).Type: ApplicationFiled: May 17, 2007Publication date: November 20, 2008Applicant: Texas Instruments IncorporatedInventors: Prema Palaniappan, Masood Murtuza, Satyendra Singh Chauhan
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Publication number: 20080280394Abstract: A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness, and then electrically coupling semiconductor dies to the formed patterns on the conductive plate. The method further includes encapsulating at least a portion of the dies and the conductive plate with an encapsulant and removing a portion of the conductive plate from the side opposite the patterned side to form conductive traces based on the formed pattern.Type: ApplicationFiled: May 7, 2008Publication date: November 13, 2008Inventors: Masood Murtuza, Satyendra Singh Chauhan, Donald C. Abbott
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Patent number: 7445960Abstract: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits, including the coupling members, in a vacuum chamber of a plasma apparatus so that the polymer-coated surface faces the plasma source. Next, a plasma is initiated; the ion mean free path is controlled so that the ions reach the wafer surface with predetermined energy. The wafer surface is then exposed to the plasma for a length of time sufficient to roughen the polymer surface, clean the polymer surface from organic contamination and improve the surface affinity to adhesion. The adhesion ability of this surface to organic underfill material is thus enhanced.Type: GrantFiled: June 14, 2007Date of Patent: November 4, 2008Assignee: Texas Instruments IncorporatedInventors: Marvin W. Cowens, Masood Murtuza, Vinu Yamunan, Charles Odegard, Phillip R. Coffman
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Publication number: 20080050860Abstract: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits, including the coupling members, in a vacuum chamber of a plasma apparatus so that the polymer-coated surface faces the plasma source. Next, a plasma is initiated; the ion mean free path is controlled so that the ions reach the wafer surface with predetermined energy. The wafer surface is then exposed to the plasma for a length of time sufficient to roughen the polymer surface, clean the polymer surface from organic contamination and improve the surface affinity to adhesion. The adhesion ability of this surface to organic underfill material is thus enhanced.Type: ApplicationFiled: June 14, 2007Publication date: February 28, 2008Inventors: Marvin Cowens, Masood Murtuza, Vinu Yamunan, Charles Odegard, Phillip Coffman
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Patent number: 7323405Abstract: A method of forming a package is disclosed, which includes steps of forming a substrate, a solder masker, and a first aperture through the solder mask. The substrate has a surface on which metal traces are formed. The solder mask covers at least a portion of the surface of the substrate. And the first aperture through the solder mask exposes a plurality of the metal traces.Type: GrantFiled: April 17, 2006Date of Patent: January 29, 2008Assignee: Texas Instruments IncorporatedInventors: Satyendra S. Chauhan, Masood Murtuza
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Patent number: 7319275Abstract: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits, including the coupling members, in a vacuum chamber of a plasma apparatus so that the polymer-coated surface faces the plasma source. Next, a plasma is initiated; the ion mean free path is controlled so that the ions reach the wafer surface with predetermined energy. The wafer surface is then exposed to the plasma for a length of time sufficient to roughen the polymer surface, clean the polymer surface from organic contamination and improve the surface affinity to adhesion. The adhesion ability of this surface to organic underfill material is thus enhanced.Type: GrantFiled: February 1, 2005Date of Patent: January 15, 2008Assignee: Texas Instruments IncorporatedInventors: Marvin W. Cowens, Masood Murtuza, Vinu Yamunan, Charles Odegard, Phillip R. Coffman