Patents by Inventor Masood Murtuza

Masood Murtuza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6396136
    Abstract: A package for a flip chip integrated circuit including an interposer with electrical interconnecting for signal, power, and ground contacts. Routing is accomplished on only two conductor layers through the use of selective planes and buses. Multiple power planes are provided on a single conductor level to support circuits having different operating voltages. A unique cavity down BGA package for a flip chip interconnected integrated circuit is provided by adhering the interposer to a thermally conductive stiffener or base, and using solder balls to attach the frame to the base and interposer. The assemblage forms a chip cavity with interconnecting vias to external BGA solder balls terminals located in the perimeter frame.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: May 28, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Navinchandra Kalidas, Masood Murtuza, Raymond W. Thompson
  • Publication number: 20010048157
    Abstract: A reliable, chip scale or flip chip semiconductor device which can be directly attached to a PC board without the use of an underfill material to absorb stress on the solder joints interconnecting the device and board is provided by a silicon chip, having the substrate thinned until the chip thickness is in the range of 50 to 250 microns, attaching a backing or cap layer with specific thermal properties to approximate those of a printed circuit board (PCB), and providing solder bump contacts attached to the input/output terminals.
    Type: Application
    Filed: February 22, 2001
    Publication date: December 6, 2001
    Inventor: Masood Murtuza
  • Publication number: 20010013654
    Abstract: A package 300 for a flip chip integrated 331 circuit including an interposer 303 with electrical interconnecting for signal, power, and ground contacts. Routing is accomplished on only two conductor layers through the use of selective planes and buses. Multiple power planes are provided on a single conductor level to support circuits having different operating voltages. A unique cavity down BGA package for a flip chip interconnected integrated circuit is provided by adhering the interposer to a thermally conductive stiffener or base 304, and using solder balls 308 to attach the frame to the base and interposer. The assemblage forms a chip cavity with interconnecting vias to external BGA solder balls terminals located in the perimeter frame.
    Type: Application
    Filed: December 22, 1999
    Publication date: August 16, 2001
    Inventors: NAVINCHANDRA KALIDAS, MASOOD MURTUZA, RAYMOND W THOMPSON
  • Patent number: 6020630
    Abstract: A semiconductor package (80) is provided that serves to support a semiconductor chip (12). A radial slot (54) is formed in an inner ring (26). Cross-slots (64) and (66) are formed in a corner member (38) of polyimide film (22). The slots (54), (64) and (66) serve to allow independent expansion of various portions of the polyimide film (22) and prevent breakage of contact leads (14), (16), (18) and (20) due to the differences in the thermal coefficient of expansion of the semiconductor material and the polyimide film material.
    Type: Grant
    Filed: January 5, 1995
    Date of Patent: February 1, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: William K. Dennis, Masood Murtuza
  • Patent number: 5586010
    Abstract: The ball grid array package (10) uses a flexible base (30) having a substantially flat center plate (34) disposed at a first level coupled to a substantially flat base plate (32) disposed at a second level. The center plate (34) is coupled to the base plate (32) by a plurality of flexible narrow straps (36-38) arranged substantially surrounding the center plate (34). The flexible base (30) accommodates the thermal expansion in the pedestal (18) caused by the powered up integrated circuit (16) so that the rest of the package does not expand and induce stress in the solder joint between the ball grid array (12) and the printed circuit board (14).
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: December 17, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Masood Murtuza, Abbas I. Attarwala