Patents by Inventor Matthew J. Kalos

Matthew J. Kalos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11281593
    Abstract: Provided are a computer program product, system, and method for using insertion points to determine locations in a cache list at which to indicate tracks in a shared cache accessed by a plurality of processors. A plurality of insertion points to a cache list for the shared cache having a least recently used (LRU) end and a most recently used (MRU) end identify tracks in the cache list. For each processor, of a plurality of processors, for which indication of tracks accessed by the processor is received, a determination is made of insertion points of the provided insertion points at which to indicate the tracks for which indication is received. The tracks are indicated at positions in the cache list with respect to the determined insertion points.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11281502
    Abstract: A method for dispatching tasks on processor cores based on memory access efficiency is disclosed. The method identifies a task and a memory area to be accessed by the task. The method may use one or more of a compiler, code knowledge, and run-time statistics to identify the memory area that is accessed by the task. The method identifies multiple processor cores that are candidates to execute the task and identifies a particular processor core from the multiple processor cores that provides most efficient access to the memory area. The method dispatches the task to execute on the particular processor core that is deemed most efficient. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 22, 2020
    Date of Patent: March 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew J. Kalos, Kevin J. Ash, Trung N. Nguyen
  • Patent number: 11281380
    Abstract: Remote copy operations are performed to copy data from a primary storage controller to a secondary storage controller, wherein input/output (I/O) requests are received at the primary storage controller from a host both via a bus interface and a network interface while the remote copy operations are in progress, and wherein consistency groups are formed during the remote copy operations to copy the data consistently. Quiescing of I/O operations performed via the bus interface are performed while a current consistency group is being replaced by a next consistency group during the remote copy operations.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: March 22, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew J. Ward, Matthew J. Kalos, Joshua J. Crawford, Carol S. Mellgren, Matthew R. Craig
  • Patent number: 11263097
    Abstract: Provided are a computer program product, system, and method for using a track format code in a cache control block for a track in a cache to process read and write requests to the track in the cache. A track format table associates track format codes with track format metadata. A determination is made as to whether the track format table has track format metadata matching track format metadata of a track staged into the cache. A determination is made as to whether a track format code from the track format table for the track format metadata in the track format table matches the track format metadata of the track staged. A cache control block for the track being added to the cache is generated including the determined track format code when the track format table has the matching track format metadata.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos, Beth A. Peterson
  • Publication number: 20220043751
    Abstract: Provided are a computer program product, system, and method for providing track access reasons for track accesses resulting in the release of prefetched cache resources for the track. A first request for a track is received from a process for which prefetched cache resources to a cache are held for a second request for the track that is expected. A track access reason is provided for the first request specifying a reason for the first request. The prefetched cache resources are released before the second request to the track is received. Indication is made in an unexpected released track list of the track and the track access reason for the first request.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Inventors: Beth Ann PETERSON, Chung Man FUNG, Matthew J. KALOS, Warren Keith STANLEY, Matthew J. WARD
  • Publication number: 20220043750
    Abstract: Provided are a computer program product, system, and method for prefetching cache resources for a write request from a host to tracks in storage cached in a cache. Cache resources held for a plurality of tracks in a write set are released before expected writes are received for the tracks in the write set. Cache resources for tracks in the write set are obtained, following the release of the cache resources, to use for expected write requests to the tracks in the write set.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Inventors: Beth Ann PETERSON, Chung Man FUNG, Matthew J. KALOS, Matthew Richard CRAIG
  • Patent number: 11243885
    Abstract: Provided are a computer program product, system, and method for providing track access reasons for track accesses resulting in the release of prefetched cache resources for the track. A first request for a track is received from a process for which prefetched cache resources to a cache are held for a second request for the track that is expected. A track access reason is provided for the first request specifying a reason for the first request. The prefetched cache resources are released before the second request to the track is received. Indication is made in an unexpected released track list of the track and the track access reason for the first request.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Chung Man Fung, Matthew J. Kalos, Warren Keith Stanley, Matthew J. Ward
  • Patent number: 11231998
    Abstract: Provided are a computer program product, system, and method for generating a chain of a plurality of write requests including a commit wait flag and plurality of write requests. The commit wait flag is set to one of an indicated first value or a second value. The commit wait flag is set to the first value to cause a storage server to process the write requests by requiring a current write request being processed to complete before transferring data for a next write request following the current write request. The commit wait flag is set to the second value to cause the storage server to process the write requests by transferring data for the next write request before completing the current write request preceding the next write request. The write request chain is sent to the storage server to apply the write requests to the storage.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: January 25, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey A. Berger, Susan K. Candelaria, Matthew J. Kalos, Beth A. Peterson, Harry M. Yudenfriend
  • Patent number: 11226899
    Abstract: Provided are a computer program product, system, and method for populating a second cache with tracks from a first cache when transferring management of the tracks from a first node to a second node. Management of a first group of tracks in the storage managed by the first node is transferred to the second node managing access to a second group of tracks in the storage. After the transferring the management of the tracks, the second node manages access to the first and second groups of tracks and caches accessed tracks from the first and second groups in the second cache of the second node. The second cache of the second node is populated with the tracks in a first cache of the first node.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Matthew J. Kalos, Brian A. Rinaldi
  • Patent number: 11204802
    Abstract: Provided are techniques for adjusting a dispatch ratio for dispatching tasks from multiple queues. The dispatch ratio is set for each queue of a plurality of queues. A number of Central Processing Unit (CPU) cycles used by tasks from each of the plurality of queues during the interval is tracked. A CPU high percentage is determined that indicates a percentage of CPU cycles used by high priority tasks. In response to determining that the CPU high percentage is below a high threshold, a new dispatch ratio is calculated that indicates an increased number of high priority tasks are to be dispatched, and the new dispatch ratio is based on the CPU high percentage, the high threshold, and a current dispatches high value. The increased number of high priority tasks are dispatched from the high priority queue based on the new dispatch ratio during a new interval.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Matthew Richard Craig, Matthew J. Kalos, Matthew G. Borlick, Micah Robison, Lokesh Mohan Gupta
  • Patent number: 11194771
    Abstract: A computer-implemented method for transferring a reserve to a target host, according to one embodiment, includes granting to a source system, by a control unit, a reserve for a volume of a storage device. A push reserve command is received from the source system. The push reserve command specifies: a transfer of the reserve to a target system, parameter data identifying the target system, and path information specifying the source system. The reserve is transferred only to the target system in response to release of the reserve by the source system.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Susan K. Candelaria, Mark P. Gardiner, Clint A. Hardy, Matthew J. Kalos, William R. White, Stephen G. Wilkins, Harry M. Yudenfriend
  • Publication number: 20210334133
    Abstract: Provided are techniques for adjusting a dispatch ratio for dispatching tasks from multiple queues. The dispatch ratio is set for each queue of a plurality of queues. A number of Central Processing Unit (CPU) cycles used by tasks from each of the plurality of queues during the interval is tracked. A CPU high percentage is determined that indicates a percentage of CPU cycles used by high priority tasks. In response to determining that the CPU high percentage is below a high threshold, a new dispatch ratio is calculated that indicates an increased number of high priority tasks are to be dispatched, and the new dispatch ratio is based on the CPU high percentage, the high threshold, and a current dispatches high value. The increased number of high priority tasks are dispatched from the high priority queue based on the new dispatch ratio during a new interval.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 28, 2021
    Inventors: Matthew Richard Craig, Matthew J. Kalos, Matthew G. Borlick, Micah Robison, Lokesh Mohan Gupta
  • Patent number: 11144475
    Abstract: A computer program product, system, and method for managing adding of accessed tracks in cache to a most recently used end of a cache list. A cache list for the cache has a least recently used (LRU) end and a most recently used (MRU) end. Tracks in the cache are indicated in the cache list. A track in the cache indicated on the cache list is accessed. A determination is made as to whether a track cache residency time since the accessed track was last accessed while in the cache list is within a region of lowest track cache residency times. A flag is set for the accessed track indicating to indicate the track at the MRU end in response to determining that the track cache residency time of the accessed track is within the region of lowest track cache residency times. The accessed track remains at a current position in the cache list before being accessed after setting the flag.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Publication number: 20210286723
    Abstract: Provided are a computer program product, system, and method for indicating extents of tracks in mirroring queues based on information gathered on tracks in extents in cache. Extent information on an extent of tracks in a cache indicated in an active cache list is processed in response to destaging a track from the active cache list to add to a demote list used to determine tracks to remove from the cache. The extent information is related to a number of modified tracks in an extent destaged from the active cache list. The extent information for the extent is used to determine one of a plurality of mirroring queues to indicate the extent including modified tracks. A mirroring queue having a higher priority than another mirroring queue is processed at a higher rate to determine extents of tracks to mirror from the cache to the secondary storage.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Publication number: 20210286729
    Abstract: Provided are a computer program product, system, and method for using mirroring cache list to demote modified tracks from cache A modified track for a primary storage stored in the cache to mirror to a secondary storage is indicated in a mirroring cache list. The mirroring cache list is processed to select modified tracks in the cache to transfer to the secondary storage that have not yet been transferred. The selected modified tracks in the cache are transferred to the secondary storage. The mirroring cache list is processed to determine modified tracks in the cache to demote from the cache.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Publication number: 20210286691
    Abstract: Provided are a computer program product, system, and method for using a mirroring cache list to mirror modified tracks for a primary storage in a cache to a secondary storage. Indication is made of a modified track for the primary storage stored in the cache in a mirroring cache list. The mirroring cache list is processed to select modified tracks in the cache to transfer to the secondary storage that have not yet been transferred. The selected modified tracks are transferred to the secondary storage. Indication of a modified track is removed from the mirroring cache list in response to demoting the modified track from the cache.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Patent number: 11119687
    Abstract: One general aspect of device reservation state synchronization in accordance with the present description, device reservation management logic ensures synchronization of reservation states of primary and secondary volumes of a mirror relationship in the event of a change in the state of the mirroring relationship such as achieving full data synchronization between the volumes. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Carol S. Mellgren, John G. Thompson
  • Publication number: 20210263781
    Abstract: A method for dispatching tasks on processor cores based on memory access efficiency is disclosed. The method identifies a task and a memory area to be accessed by the task. The method may use one or more of a compiler, code knowledge, and run-time statistics to identify the memory area that is accessed by the task. The method identifies multiple processor cores that are candidates to execute the task and identifies a particular processor core from the multiple processor cores that provides most efficient access to the memory area. The method dispatches the task to execute on the particular processor core that is deemed most efficient. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: February 22, 2020
    Publication date: August 26, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew J. Kalos, Kevin J. Ash, Trung N. Nguyen
  • Patent number: 11093395
    Abstract: Provide a computer program product, system, and method for adjusting insertion points used to determine locations in a cache list at which to indicate tracks based on number of tracks added at insertion points. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end. Each insertion point of the insertion points identifies a track in the cache list. A plurality of tracks are indicated at positions in the cache list with respect to insertion points. For each track indicated at an insertion point of the insertion points, at least one insertion point counter for at least one insertion point with respect to the insertion point at which the track is indicated is incremented. A plurality of the insertion points are adjusted to point to different tracks in the cache list based on insertion point counters for the insertion points.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11086784
    Abstract: Provided are a computer program product, system, and method for invalidating track format information for tracks in cache. Demoted tracks demoted from the cache are indicated in a demoted track list. Track format information is saved for the demoted tracks. The track format information indicates a layout of data in the demoted tracks, wherein the track format information for the demoted tracks is used when the demoted tracks are staged back into the cache. An operation is initiated to invalidate a metadata track of the metadata tracks in the storage. Demoted tracks indicated in the demoted track list having metadata in the metadata track to invalidate are removed. The track format information for the demoted tracks having metadata in the metadata track to invalidate is removed.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos