Patents by Inventor Matthew J. Kalos

Matthew J. Kalos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11074185
    Abstract: Provided are a computer program product, system, and method for adjusting a number of insertion points used to determine locations in a cache list at which to indicate tracks. Tracks added to the cache are indicated in a cache list. The cache list has a least recently used (LRU) end and a most recently used (MRU) end. In response to indicating in a cache list an insertion point interval number of tracks in the cache in a cache list, setting an insertion point to indicate one of the tracks of the insertion point interval number of tracks indicated in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11068415
    Abstract: Provided are a computer program product, system, and method for using insertion points to determine locations in a cache list at which to move processed tracks. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end, wherein each insertion point of the insertion points identifies a track in the cache list. An insertion point of the insertion points is determined at which to move the processed track in response to determining that a processed track is indicated to move to the MRU end. The processed track is indicated at a position in the cache list with respect to the determined insertion point.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11048631
    Abstract: Provided are a computer program product, system, and method for maintaining cache hit ratios for insertion points into a cache list to optimize memory allocation to a cache. A plurality of insertion points to a cache list for the cache each identify a track in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list that are to be indicated at the MRU end of the cache list. Indication is made of cache hits for each of the insertion points used to indicate locations in the cache list for tracks accessed while indicated in the cache list. The cache hits indicated for the insertion points are to indicate whether to increase or decrease a size of the cache.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Publication number: 20210191643
    Abstract: A computer-implemented method according to one embodiment includes identifying a request to migrate data associated with a volume from a source storage pool having a first rank extent size to a destination storage pool having a second rank extent size smaller than the first rank extent size, creating a correspondence between logical volume extents of the volume and physical offset locations within rank extents of the source storage pool, and migrating data from one or more ranks of the source storage pool to one or more ranks of the destination storage pool, utilizing the correspondence between the logical volume extents of the volume and the physical offset locations within the rank extents of the source storage pool.
    Type: Application
    Filed: March 10, 2021
    Publication date: June 24, 2021
    Inventors: Hui Zhang, Clint A. Hardy, Karl A. Nielsen, Matthew J. Kalos, Qiang Xie
  • Patent number: 11036641
    Abstract: Provided are a computer program product, system, and method for invalidating track format information for tracks demoted from cache. Demoted tracks demoted from the cache are indicated in a demoted track list. Track format information is saved for the demoted tracks. The track format information indicates a layout of data in the demoted tracks, wherein the track format information for the demoted tracks is used when the demoted tracks are staged back into the cache. An operation is initiated to invalidate a metadata track of the metadata tracks in the storage. Demoted tracks indicated in the demoted track list having metadata in the metadata track to invalidate are removed. The track format information for the demoted tracks having metadata in the metadata track to invalidate is removed.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 15, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos
  • Publication number: 20210157635
    Abstract: Provided are a computer program product, system, and method for determining an optimum number of threads to make available per core in a multi-core processor complex to execute tasks. A determination is made of a first processing measurement based on threads executing on the cores of the processor chip, wherein each core includes circuitry to independently execute a plurality of threads. A determination is made of a number of threads to execute on the cores based on the first processing measurement. A determination is made of a second processing measurement based on the threads executing on the cores of the processor chip. A determination is made of an adjustment to the determined number of threads to execute based on the second processing measurement resulting in an adjusted number of threads. The adjusted number of threads on the cores is utilized to execute instructions.
    Type: Application
    Filed: November 21, 2019
    Publication date: May 27, 2021
    Inventors: Brian Anthony Rinaldi, Lokesh M. Gupta, Kevin J. Ash, Matthew J. Kalos, Trung N. Nguyen, Clint A. Hardy, Louis A. Rasor
  • Patent number: 11016691
    Abstract: A computer-implemented method according to one embodiment includes identifying a request to migrate data associated with a volume from a source storage pool having a first rank extent size to a destination storage pool having a second rank extent size smaller than the first rank extent size, creating a correspondence between logical volume extents of the volume and physical offset locations within rank extents of the source storage pool, and migrating data from one or more ranks of the source storage pool to one or more ranks of the destination storage pool, utilizing the correspondence between the logical volume extents of the volume and the physical offset locations within the rank extents of the source storage pool.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hui Zhang, Clint A. Hardy, Karl A. Nielsen, Matthew J. Kalos, Qiang Xie
  • Patent number: 11016692
    Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Brian A. Rinaldi, Kyler A. Anderson, Matthew J. Kalos
  • Patent number: 11010295
    Abstract: A cache hit is generated, in response to receiving an input/output (I/O) command over a bus interface. An update for a metadata track is stored in a buffer associated with a central processing unit (CPU) that processes the I/O command, in response to generating the cache hit. The metadata track is asynchronously updated from the buffer with the stored update for the metadata track in the buffer.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: May 18, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos
  • Patent number: 10983913
    Abstract: In response to determining, by a storage controller, that a first process is to perform a write operation, a customer data track in a cache is configured for exclusive access while waiting for the write operation on the customer data track to be performed by the first process. In response to configuring the customer data track for the exclusive access, a copy of a metadata track is generated, wherein the metadata track stores metadata information of the customer data track and is configured for shared access. The copy of the metadata track is configured to provide exclusive access to a second process to perform operations on the copy of the metadata track, wherein the first process is able to perform the write operation on the customer data track that causes the metadata track to be updated while the second process performs the operations on the copy of the metadata track.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos, Beth A. Peterson
  • Patent number: 10983708
    Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices by a host accessing logical devices provisioned with a capacity from physical devices managed by a control unit. The host establishes with the control unit an association of logical devices and alias addresses assigned to the logical devices, wherein the alias addresses are associated with an alias management group. Alias address pool information is generated indicating each of the logical devices and their assigned alias addresses indicated in the association. The host uses from the alias address pool information any one of the alias addresses in the alias address pool information to access any of the logical devices associated with the same alias management group as the alias address.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Susan K. Candelaria, Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Dale F. Riedy, Richard A. Ripberger, Harry M. Yudenfriend
  • Publication number: 20210109670
    Abstract: A method according to one embodiment includes identifying a request to migrate data associated with a volume from a source storage pool to a destination storage pool, identifying volume segment table (VST) entries corresponding to rank extents within the source storage pool containing the data, allocating and synchronizing small VSTs for the identified VST entries within the volume, allocating one or more rank extents within the destination storage pool, transferring the data associated with the volume from the rank extents within the source storage pool containing the data to the one or more rank extents in the one or more ranks of the destination storage pool, updating the small VSTs to correspond to the transferred data in the one or more rank extents in the one or more ranks of the destination storage pool, and freeing the data from the one or more rank extents within the source storage pool.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Inventors: Hui Zhang, Clint A. Hardy, Karl A. Nielsen, Matthew J. Kalos, Qiang Xie
  • Patent number: 10970178
    Abstract: Provided are a computer program product, system, and method for generating a health condition message on a health condition detected at a first server to send to a host system accessing the first server. A determination is made of a health condition with respect to access to a first storage. A determination is made of an estimated Input/Output (I/O) delay to access the first storage resulting from the determined health condition. A health condition message is generated indicating the estimated I/O delay. The health condition message is transmitted to the host system, wherein the host system uses the estimated I/O delay to determine whether to perform a swap operation to redirect host I/O requests to data from the first server to a second server.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clint A. Hardy, Matthew J. Kalos
  • Publication number: 20210072918
    Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Brian A. Rinaldi, Kyler A. Anderson, Matthew J. Kalos
  • Patent number: 10942835
    Abstract: Provided are a computer program product, system, and method for processing a health condition message on a health condition to determine whether to perform a swap operation. A health condition message is received from a first server indicating an estimated Input/Output (I/O) delay to access a first storage resulting from a health condition experienced at the first server. A determination is made as to whether the estimated I/O delay exceeds a threshold response time for the first storage. A swap operation is performed to redirect I/O requests to data from the first server to the second server to access the data at the second storage in response to determining that the estimated I/O delay exceeds the threshold response time.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clint A. Hardy, Matthew J. Kalos
  • Publication number: 20210049108
    Abstract: A computer program product, system, and method for managing adding of accessed tracks in cache to a most recently used end of a cache list. A cache list for the cache has a least recently used (LRU) end and a most recently used (MRU) end. Tracks in the cache are indicated in the cache list. A track in the cache indicated on the cache list is accessed. A determination is made as to whether a track cache residency time since the accessed track was last accessed while in the cache list is within a region of lowest track cache residency times. A flag is set for the accessed track indicating to indicate the track at the MRU end in response to determining that the track cache residency time of the accessed track is within the region of lowest track cache residency times. The accessed track remains at a current position in the cache list before being accessed after setting the flag.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: Lokesh M. GUPTA, Kyler A. ANDERSON, Kevin J. ASH, Matthew J. KALOS
  • Publication number: 20210049109
    Abstract: Provided are a computer program product, system, and method for managing adding of accessed tracks to a cache list based on accesses to different regions of the cache list. A cache has a least recently used (LRU) end and a most recently used (MRU) end. A determination is made of a high access region of tracks from the MRU end of the cache list based on a number of accesses to the tracks in the high access region. A flag is set for an accessed track, indicating to indicate the accessed track at the MRU end upon processing the accessed track at the LRU end, in response to the determining the accessed track is in the high access region. After the setting the flag, the accessed track remains at a current position in the cache list before being accessed.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: Lokesh M. GUPTA, Kyler A. ANDERSON, Kevin J. ASH, Matthew J. KALOS
  • Patent number: 10922268
    Abstract: A computer-implemented method according to one embodiment includes identifying a request to migrate data associated with a volume from a source storage pool that has a first rank extent size to a destination storage pool that has a second rank extent size greater than the first rank extent size. Additionally, the method includes creating a correspondence between logical volume extents of the volume and physical offset locations within rank extents of the destination storage pool. Further, the method includes migrating data from one or more ranks of the source storage pool to one or more ranks of the destination storage pool, according to the correspondence between the logical volume extents of the volume and the physical offset locations within the rank extents of the destination storage pool.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: February 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Clint A. Hardy, Hui Zhang, Karl A. Nielsen, Qiang Xie, Matthew J. Kalos
  • Publication number: 20210042231
    Abstract: Provide a computer program product, system, and method for adjusting insertion points used to determine locations in a cache list at which to indicate tracks based on number of tracks added at insertion points. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end. Each insertion point of the insertion points identifies a track in the cache list. A plurality of tracks are indicated at positions in the cache list with respect to insertion points. For each track indicated at an insertion point of the insertion points, at least one insertion point counter for at least one insertion point with respect to the insertion point at which the track is indicated is incremented. A plurality of the insertion points are adjusted to point to different tracks in the cache list based on insertion point counters for the insertion points.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Publication number: 20210042241
    Abstract: Provided are a computer program product, system, and method for using insertion points to determine locations in a cache list at which to indicate tracks in a shared cache accessed by a plurality of processors. A plurality of insertion points to a cache list for the shared cache having a least recently used (LRU) end and a most recently used (MRU) end identify tracks in the cache list. For each processor, of a plurality of processors, for which indication of tracks accessed by the processor is received, a determination is made of insertion points of the provided insertion points at which to indicate the tracks for which indication is received. The tracks are indicated at positions in the cache list with respect to the determined insertion points.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos